LTC1654
PI FU CTIO S
X
1
/X
1/2
B, X
1
/X
1/2
A (Pins 1, 8):
The Gain of 1 or Gain of
1/2 Pin. When this pin is tied to V
OUT
, the output range will
be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when
REFLO = 0V). When this pin is tied to REFLO, the output
range will be REFLO to REFHI (0V to REFHI when REFLO
= 0V). These pins should not be left floating.
CLR (Pin 2):
The Asynchronous Clear Input.
SCK (Pin 3):
The TTL Level Input for the Serial Interface
Clock.
SDI (Pin 4):
The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 allows
either a 24-bit or 32-bit word. When a 24-bit word is used,
the first 8 bits are control and address followed by 16 data
bits. The last two of the 16 data bits are don’t cares. When
a 32-bit word (required for daisy-chain operation) is used,
the first 8-bits are don’t cares and the following 24-bits are
as above.
CS/LD (Pin 5):
The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
DGND/AGND (Pins 6, 12):
Digital and Analog Grounds.
SDO (Pin 7):
The output of the shift register that becomes
valid on the rising edge of the serial clock.
V
OUT A/B
(Pins 9, 15):
The Buffered DAC Outputs.
REFHI A/B (Pins 10, 14):
The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to V
OUT
.
REFLO A/B (Pins 11, 13):
The Reference Low Inputs of the
LTC1654. These inputs can swing up to V
CC
– 1.5V.
V
CC
(Pin 16):
The Positive Supply Input. 2.7V
≤
V
CC
≤
5.5V.
Requires a 0.1µF bypass capacitor to ground.
TI I G DIAGRA S
t
2
t
1
SCK
t
9
SDI
X
X
C3
B0
X
X
t
5
CS/LD
t
8
SDO
X
(PREVIOUS
WORD)
X
C3
X
X
X
CURRENT WORD
1654 TD01
6
W
U
U
UW
U
t
6
t
4
t
3
t
7
1654fb
LINER [ LINEAR TECHNOLOGY ]
