LTC1646
U
W U U
APPLICATIO S I FOR ATIO
4. Programmable foldback current limit: a programmable
analog current limit with a value that depends on the
output voltage. If the output is shorted to ground, the
current limit drops to keep power dissipation and
supply glitches to a minimum.
The main 3.3V and 5V inputs to the LTC1646 come from
the medium length power pins. The long 3.3V, 5V connec-
tor pins are shorted to the medium length 5V and 3.3V
connector pins on the CPCI plug-in card and provide early
power for the LTC1646’s precharge circuitry, the V(I/O)
pull-up resistors and the PCI bridge chip. The BD_SEL#
signal is connected to the OFF/ON pin while the PWRGD
pin is connected to the HEALTHY# signal. The HEALTHY#
signal is combined with the PCI_RST# signal on-chip to
generate the LOCAL_PCI_RST# signal which is available
at the RESETOUT pin.
5. Dual-level,programmable5Vand3.3Vcircuitbreakers:
this feature is enabled when the TIMER pin voltage
exceeds 1.25V. If either supply exceeds current limit
for more than 21µs, the circuit breaker will trip, the
supplies will be turned off, and the FAULT pin is pulled
low. In the event that either supply exceeds three times
the set current limit, all supplies will be turned off and
the FAULT pin is pin is pulled low without delay.
The power supplies are controlled by placing external
N-channel pass transistors in the 3.3V and 5V power
paths.
6. 15V high side drive for external 3.3V and 5V N-channel
MOSFETs.
Resistors R1 and R2 provide current fault detection and
R5 and C1 provide current control loop compensation.
Resistors R3 and R4 prevent high frequency oscillations
in Q1 and Q2.
7. PWRGD output: monitors the voltage status of the
supply voltages.
8. PCI_RST# combined on-chip with HEALTHY# to create
LOCAL_PCI_RST# output. If HEALTHY# deasserts,
LOCAL_PCI_RST# is asserted independent of
PCI_RST#.
When the CPCI card is inserted, the long 5V and 3.3V
connector pins and GND pins make contact first. The
LTC1646’s precharge circuit biases the bus I/O pins to 1V
during this stage of the insertion (Figure 2). The 5V and
3.3V medium length pins make contact during the next
stage of insertion, but the slot power is disabled as long
as the OFF/ON pin is pulled high by the 1.2k pull-up
resistortoV(I/O). Duringthefinalstageofboardinsertion,
the BD_SEL# short connector pin makes contact and the
OFF/ON pin can be pulled low. This enables the pass
transistors to turn on and a 5µA current source is con-
nected to the TIMER pin.
9. Precharge output: on-chip reference and amplifier pro-
vide 1V for biasing bus I/O connector pins during CPCI
card insertion and extraction.
10. Space saving 16-pin SSOP package.
PCI Power Requirements
CPCIsystemsmayrequireuptofourpowerrails:5V,3.3V,
12V and –12V. The LTC1646 is designed for CPCI applica-
tions which only use the 5V and/or 3.3V supplies. The
tolerance of the supplies as measured at the components
on the plug-in card is summarized in Table 1.
The current in each pass transistor increases until it
reaches the current limit for each supply. The 5V and 3.3V
supplies are then allowed to power up based on one of the
following power-up rates:
Table 1. PCI Power Supply Requirements
SUPPLY
5V
TOLERANCE
5V ±5%
CAPACITIVE LOAD
<3000µF
ILIMIT(5V)
ILIMIT(3V)
dV 13µA
=
,or =
,or =
(1)
dt
C1
CLOAD(5VOUT)
CLOAD(3VOUT)
3.3V
3.3V ±0.3V
<3000µF
whichever is slower.
Current limit faults are ignored while the TIMER pin
voltage is ramping up and is less than 1.25V. Once both
supply voltages are within tolerance, HEALTHY# will pull
Power-Up Sequence
The LTC1646 is specifically designed for hot swapping
CPCI boards. The typical application is shown in Figure 1.
low and LOCAL_PCI_RST# is free to follow PCI_RST#.
1646fa
10
Linear [ Linear ]
