LTC1642A
U
W
U U
APPLICATIO S I FOR ATIO
Overvoltage Protection
Once the CRWBR timer trips the LTC1642A latches off:
after the overvoltage clears GATE and FAULT remain at
groundandCRWBRcontinuessourcing1.5mA. Torestart
the part after the overvoltage clears, hold the ON pin low
foratleast2µsandthenbringithigh.TheGATEvoltagewill
begin ramping up one system timing cycle later. The part
will restart itself if FAULT and ON are connected.
The LTC1642A can protect a load from overvoltages by
turning off the pass transistor if the supply voltage ex-
ceedsanadjustablelimit, andbytriggeringacrowbarSCR
if the overvoltage lasts longer than an adjustable time. The
part can also be configured to automatically restart when
the overvoltage clears.
Figure 9 shows typical waveforms when the divider is
driven from VCC. The OV comparator goes high at time 1,
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s compara-
tor trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5theCRWBRtimertrips;FAULTgoeslowandtheCRWBR
pin begins sourcing 1.5mA. Even after OV falls below
1.22V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON
goes low at time 7, and GATE begins charging at time 8,
one RST TMR cycle after FAULT goes high.
The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunt-
ing the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.22V bandgap ref-
erence, two current sources, and a timer at the CRWBR
pin.WhenVCCexceeds(1+R6/R5)•1.22Vthecomparator’s
output goes high and internal logic turns off Q1 and starts
the timer. This timer has a 0.410V threshold and uses the
CRWBR pin; when CRWBR reaches 0.410V the timer
comparator trips, and the current sourced from VCC in-
creases to 1.5mA. Emitter follower Q2 boosts this current
to trigger crowbar SCR Q3. The ramp time ∆t needed to
trip the comparator is:
Figure 10 shows typical waveforms when the OV divider is
driven from the N-Channel’s output side. Because the
voltagedrivingthedividercollapsesaftertheOVcompara-
tortrips,FAULTstayshighandCRWBRstaysnearground,
which prevents the pin from triggering an SCR. The GATE
voltage begins ramping up after a RST TMR timing cycle.
tCRWBR = 9.1(ms/µF) C5
R2
Q1
V
0.015Ω
FDS6630A
IN
To disable overvoltage protection completely, tie the OV
andCRWBRpinstoGND.Forovervoltageprotectionatthe
GATE pin, but without latch off or a crowbar SCR such as
Q3 in Figure 1, tie CRWBR to GND.
12V
V
OUT
2.5A
+
R6
127k
1%
16
15
C
LOAD
R3
V
SENSE
CC
100Ω
9
OV
14
GATE
R5
12.4k
1%
t
1
t
t
t
t
t
t
7
t
R4
330Ω
C2
D1
1N4705
18V
2
3
4
5
6
8
IN
20V/DIV
2V/DIV
LTC1642A
0.047µF
OV
Q2
2N2222
4
ON
Q3
MCR12DC
GATE
50V/DIV
6
1
FAULT
CRWBR
OUT
CRWBR
RST TMR
ON
20V/DIV
1V/DIV
2V/DIV
20V/DIV
RST TMR
3
GND
8
C1
0.33µF
* ADD 220Ω RESISTOR IF
USING A SENSITIVE-GATE SCR
C5
0.01µF
ALL RESISTORS ±5% UNLESS NOTED
FAULT
20V/DIV
OV COMPARATOR TRIPS AT V = 13.85V
IN
RESET TIME = 200ms
CROWBAR DELAY TIME = 90µs
100ms/DIV
1642a F09
1642a F08
Figure 9. Overvoltage Timing (Input Side)
Figure 8. Overvoltage Protection Circuitry
1642af
12
Linear [ Linear ]
