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1446LI 参数 Datasheet PDF下载

1446LI图片预览
型号: 1446LI
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道12位轨至轨微DAC的采用SO - 8 [Dual 12-Bit Rail-to-Rail Micropower DACs in SO-8]
分类和应用:
文件页数/大小: 12 页 / 168 K
品牌: Linear [ Linear ]
 浏览型号1446LI的Datasheet PDF文件第1页浏览型号1446LI的Datasheet PDF文件第2页浏览型号1446LI的Datasheet PDF文件第3页浏览型号1446LI的Datasheet PDF文件第4页浏览型号1446LI的Datasheet PDF文件第6页浏览型号1446LI的Datasheet PDF文件第7页浏览型号1446LI的Datasheet PDF文件第8页浏览型号1446LI的Datasheet PDF文件第9页  
LTC1446/LTC1446L  
W
U
TYPICAL PERFORMANCE CHARACTERISTICS  
LTC1446 Supply Current vs  
Temperature  
LTC1446L Supply Current  
vs Temperature  
LTC1446L Supply Current vs Logic  
Input Voltage  
700  
1.2  
1.1  
970  
960  
950  
940  
930  
920  
910  
900  
690  
680  
670  
660  
650  
640  
630  
620  
V
= 3.3V  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
CC  
CC  
V
V
= 5.5V  
= 5V  
CC  
V
= 3V  
CC  
CC  
V
= 2.7V  
V
= 4.5V  
CC  
25 45  
TEMPERATURE (°C)  
55 35 –15  
5
65 85 105 125  
1.0  
1.5  
2.0  
2.5  
3.0  
0.5  
–55 –35 –15  
5
25 45 65 85 105 125  
LOGIC INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
1446/46L G12  
1446/46L G10  
1446/46L G11  
Large Signal Transient Response  
V
OUT  
(2V/DIV)  
CS/LD  
(5V/DIV)  
TIME (10µs/DIV)  
1446L G13  
U
U
U
PIN FUNCTIONS  
DOUT: The output of the shift register which becomes valid  
CLK: The Serial Interface Clock.  
on the rising edge of the serial clock.  
DIN: The Serial Interface Data.  
GND: Ground.  
CS/LD: The Serial Interface Enable and Load Control.  
When CS/LD is low the CLK signal is enabled, so the data  
can be clocked in. When CS/LD is pulled high data is  
loaded from the shift register into the DAC registers,  
updating the DAC outputs.  
VOUT A,VOUT B: Buffered DAC Outputs.  
VCC: Positive Supply Input.  
4.5V VCC 5.5V (LTC1446), 2.7V VCC 5.5V  
(LTC1446L). Requires a 0.1µF bypass capacitor to  
ground.  
5
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