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1402 参数 Datasheet PDF下载

1402图片预览
型号: 1402
PDF下载: 下载PDF文件 查看货源
内容描述: 串行12位, 2.2Msps采样ADC ,带有关断 [Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown]
分类和应用:
文件页数/大小: 24 页 / 281 K
品牌: Linear [ Linear ]
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LTC1402  
U
W U U  
APPLICATIONS INFORMATION  
0000 0000 0000 and 0000 0000 0001. For full-scale ad-  
justment in Figures 10a and 10b, apply an input voltage of  
The LTC1402 has differential inputs to minimize noise  
coupling. Common mode noise on the AIN+ and AINleads  
will be rejected by the input CMRR. The AINinput can be  
usedasagroundsensefortheAIN+ input;theLTC1402will  
hold and convert the difference voltage between AIN+ and  
AIN. The leads to AIN+ (Pin 3) and AIN(Pin 4) should be  
kept as short as possible. In applications where this is not  
possible, the AIN+ and AINtraces should be run side-by-  
side to cancel noise coupling.  
+
2.0465V (FS – 1.5LSBs) to AIN and adjust R5 until the  
output code flickers between 1111 1111 1110 and 1111  
1111 1111.  
BOARD LAYOUT AND BYPASSING  
Wire wrap boards are not recommended for high resolu-  
tion and/or high speed A/D converters. To obtain the best  
performance from the LTC1402, a printed circuit board  
with ground plane is required. Layout for the printed  
circuit board should ensure that digital and analog signal  
linesareseparatedasmuchaspossible. Inparticular, care  
should be taken not to run any digital track alongside an  
analog signal track.  
SUPPLY BYPASSING  
High quality, low series resistance 10µF ceramic bypass  
capacitors should be used at the VDD and VREF pins.  
Surface mount ceramic capacitors such as Murata  
GRM235Y5V106Z016 provide excellent bypassing in a  
small board space. Alternatively, 10µF tantalum capaci-  
tors in parallel with 0.1µF ceramic capacitors can be used.  
Bypass capacitors must be located as close to the pins as  
possible. The traces connecting the pins and the bypass  
capacitorsmustbekeptshortandshouldbemadeaswide  
as possible.  
An analog ground plane separate from the logic system  
ground should be established under and around the ADC.  
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all  
other analog grounds should be connected directly to an  
analog ground plane. Pin 9 (OGND) should be connected  
near Pin13 (DGND), where the analog ground plane ties to  
the logic system ground. The VREF bypass capacitor and  
the DVDD bypass capacitor should also be connected to  
this analog ground plane, see Figure 11. No other digital  
groundsshouldbeconnectedtothisanaloggroundplane.  
Low impedance analog and digital power supply common  
returnsareessentialtolownoiseoperationoftheADCand  
the foil width for these tracks should be as wide as  
possible. The traces connecting the pins and bypass  
capacitorsmustbekeptshortandshouldbemadeaswide  
as possible.  
POWER-DOWN MODES  
Upon power-up, the LTC1402 is initialized to the active  
stateandisreadyforconversion. TheNapandSleepMode  
waveforms showthepower-downmodesfortheLTC1402.  
TheSCKandCONVinputscontrolthepower-downmodes  
(see Timing Diagrams). Two rising edges at CONV, with-  
out any intervening rising edges at SCK, put the LTC1402  
in Nap mode and the power drain drops from 90mW to  
12  
3V TO 5V  
OV  
D
DD  
10  
3
+
DIGITAL  
SYSTEM  
LTC1402  
AGND1  
A
OUT  
OGND  
9
IN  
A
V
AGND2  
6
V
AV  
DV DGND  
DD  
IN  
REF  
DD  
1
SS  
SYSTEM  
GROUND  
ANALOG  
INPUT  
CIRCUITRY  
4
+
5
14  
10µF  
2
12  
10µF  
13  
1402 F11  
10µF  
ANALOG GROUND PLANE  
Figure 11. Power Supply Grounding Practice  
15  
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