LTM4641
APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES
Overcurrent Foldback Protection
If any nonlatching fault conditions occur, internal circuitry
pullsHYSTlowandswitchingactionisinhibited.Thepower
stagewillbehighimpedanceuntiltheaforementionedstart-
upconditionsaremet.Ifanylatchofffaultconditionoccurs,
HYST is latched low and switching action is inhibited until
the LTM4641 is unlatched (by pulling LATCH logic high)
TheLTM4641hasovercurrentprotection(OCP). Inashort
circuit from V
to GND, the internal current comparator
OUT
threshold folds back during a short to reduce the output
current, progressively down to about one-third of its
normal value (down from 24A to 8A, typical). To recover
from foldback current limit, the excessive load or low
impedance short needs to be removed. Foldback current
limiting action is disabled during soft-start and tracking
start-up.
or V power is recycled (with INTV falling below 2V).
INL
CC
The LTM4641 can be configured to restart autonomously
after an adjustable timeout delay time—instead of ex-
hibiting latchoff behavior—by leaving LATCH logic high
(connected to INTV , for example) and setting the hiccup
CC
Power Good Indicator and Latching Output
Overvoltage Protection
retry timeout delay time with C
reminded that use of C
(see Figure 47). Be
TMR
also introduces POR behavior,
TMR
yet the POR and timeout delay timers operate indepen-
dently. The effect of C can be negated by pulling the
Internalovervoltageandundervoltagecomparatorsassert
theopen-drainPGOODoutputlogiclowiftheoutputvoltage
is outside 10% of nominal, after a 12μs “blanking time”.
The blanking time allows the output voltage to experience
brief excursions (due to large load-step transients, for
example) without nuisance-tripping PGOOD. The PGOOD
output is deasserted without any deliberate blanking time
when the output voltage returns to (or enters) the power
good window, with ~2% to 3% of hysteresis. If the feed-
back voltage exceeds the upper PGOOD valid limit, the
TMR
TMR pin to INTV .
CC
Switching action will be inhibited if any of the following
occur:
•ꢀ RUNꢀisꢀlessꢀthanꢀ1.15Vꢀ(nominal;ꢀ0.8V,ꢀovertemperature).ꢀ
Not a fault; no POR or timeout delay time is imposed.
•ꢀ Anyꢀnonlatchingꢀfaultsꢀoccur:
a. DRV falls below 3.35V. In the Figure 45 and
CC
synchronous power MOSFET, M , turns on (with no
BOT
Figure46circuits,thishappensatV <4V,maximum.
INL
blanking time)—to try sinking current from the output to
GND,throughLTM4641’spowerinductor—untiltheoutput
voltage returns to the PGOOD valid region. If the output
b. UVLO falls below 0.5V.
c. IOVRETRY exceeds 0.5V.
voltage exceeds an adjustable threshold set by OV
,
PGM
d. TEMP falls below 438mV when OTBH is electrically
open circuit.
whose default value corresponds to 11% above nominal,
the LTM4641 pulls its CROWBAR output logic high imme-
diately(500nsresponsetime,maximum)andlatchesoffits
outputvoltage:thepowerstagebecomeshighimpedance,
•ꢀ Anyꢀlatchoffꢀfaultsꢀoccur:
a. OVLO exceeds 0.5V.
with both M
and M
turning off and staying latched
TOP
BOT
off; furthermore, MSP’s gate is pulled to V potential
b. CROWBAR exceeds 1.5V.
INH
rapidly (<2.6μs response time, maximum), to disconnect
the input source voltage from the module’s power stage.
Restarting regulation after a latchoff event has occurred
is explained in detail in the Start-Up/Shutdown section.
c. TEMP falls below 438mV when OTBH is logic low.
The LTM4641’s state diagram is provided in Appendix B.
Start-up and shutdown mechanisms for any given op-
erating scenario are identified in the state diagram. The
The behavior of turning on the synchronous MOSFET dur-
ing detection of an output overvoltage is a rudimentary
andpopularkindofoutputovervoltageprotectionscheme
commonly found in the power supply and semiconductor
control IC industry. It can provide mediocre overvoltage
TEMP andDRV pinshavebuilt-in hysteresis. The UVLO,
CC
IOVRETRY, OVLO, TEMP, CROWBAR and DRV pins con-
CC
nect to comparators with built-in glitch immunity, with
characteristics indicated in Figure 12.
4641f
32
Linear [ Linear ]
