LTM4616
APPLICATIONS INFORMATION
Therefore R = 10k and R = 6.65k in Figure 5. Figure 6
becomes high, and 3.3V output starts its shutdown after
the PGOOD signal of 1.5V output becomes low. This can
be applied to systems that require voltage sequencing
between the core and sub-power supplies. The PGOOD
pull-up resistor value can be determined as follows:
TB
TA
shows the output voltage for coincident tracking.
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR
TB
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
SV – VRUN
IN
RPGOOD(MAX)
=
IPGOOD(MAX)
For example: MR = 3.3V/ms and SR = 1.5V/ms. Then
Forexample:V =SV =5V,V
PGOOD(MAX)
value of 100k provides some margin.
=1.7VandI
PGOOD(MAX)
IN
IN
RUN
R
= 22.1k. Solve for R to equal to 4.87k.
TB
TA
= 30µA. Solve for R
to equal 110k. Selecting a
Forapplicationsthatdonotrequiretrackingorsequencing,
simply tie the TRACK pin to SV to let RUN control the
IN
turn on/off. Connecting TRACK to SV also enables the
IN
Stability Compensation
~100µs of internal soft-start during start-up.
The module has already been internally compensated
for all output voltages. Table 2 is provided for most ap-
plication requirements. LTpowerCAD is available for fine
adjustments to the control loop.
MASTER OUTPUT
SLAVE OUTPUT
Output Margining
For a convenient system stress test on the LTM4616’s
output, the user can program each output to 5%, 10%
or 15% of its normal operational voltage. Margining
can be disabled by connecting the MGN pin to a voltage
divider as shown in Figure 5. When the MGN pin is <0.3V,
it forces negative margining, in which the output voltage
TIME
4616 F06
Figure 6. Output Voltage Coincident Tracking
is below the regulation point. When MGN is >V – 0.3V,
IN
the output voltage is forced above the regulation point.
The MGN pin with a voltage divider is driven with a small
tri-stategateasshowninFigure18forthreemarginstates,
(High, Low, andNoMargin). Theamountofoutputvoltage
margining is determined by the BSEL pin. When BSEL is
low, it’s 5%. When BSEL is high, it’s 10%. When BSEL is
floating, it’s 15%. When margining is active, the internal
output overvoltage and undervoltage comparators are
disabled and PGOOD remains high.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. As shown
in Figure 20, the sequencing function can be realized in a
dualoutputapplicationbycontrollingtheRUNpinsandthe
PGOOD signals from each other. The 1.5V output begins
its soft starting after the PGOOD signal of 3.3V output
4616fe
17
For more information www.linear.com/LTM4616
LINEAR_DIMENSIONS [ Linear Dimensions ]
