LTC2378-16
applicaTions inForMaTion
TIMING AND CONTRO5
DIGITA5 INTERFACE
The LTC2378-16 has a serial digital interface. The flexible
CNV Timing
OV supply allows the LTC2378-16 to communicate with
DD
The LTC2378-16 conversion is controlled by CIV. A ris-
ing edge on CIV will start a conversion and power up the
LTC2378-16.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CIV should be driven by a clean low jitter
signal. Converter status is indicated by the ꢀUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CIV should occur within 4±ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2378-16 powers down and begins acquiring the
input signal.
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
4±MHz, a 1Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2378-16 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2378-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPꢁ bus or are daisy-chained.
Internal Conversion Clock
The LTC2378-16 has an internal clock that is trimmed to
achieveamaximumconversiontimeof527ns.Withamin-
imum acquisition time of 46±ns, throughput performance
of 1Msps is guaranteed without any external adjustments.
6
5
Auto Power-Down
I
VDD
4
3
2
1
0
The LTC2378-16 automatically powers down after a con-
version has been completed and powers up once a new
conversion is initiated on the rising edge of CIV. During
power down, data from the last conversion can be clocked
out. To minimize power dissipation during power down,
disableSDOandturnoffSCK.Theautopower-downfeature
will reduce the power dissipation of the LTC2378-16 as
the sampling frequency is reduced. Since power is con-
sumedonlyduringaconversion, theLTC2378-16remains
powered-downforalargerfractionoftheconversioncycle
I
REF
I
OVDD
0
100 200 300 400 500 600 700 800 9001000
SAMPLING RATE (kHz)
237816 F12
Figure 120 Power Supply Current of the 5TC2378-16
Versus Sampling Rate
(t ) at lower sample rates, thereby reducing the average
CYC
power dissipation which scales with the sampling rate as
shown in Figure 12.
237816f
15
LINEAR_DIMENSIONS [ Linear Dimensions ]
