LTC2995
PIN FUNCTIONS
+
+
D : Diode Sense Current Source. D sources the remote
TO1: Temperature Logic Output 1. Open drain logic output
+
diode sensing current. Connect D to the anode of the re-
thatpullstoGNDwhenV
crossesthethresholdvoltage
PTAT
motesensordevice.Itisrecommendedtoconnecta470pF
on pin VT1 with a polarity set by the PS pin (see Table 3
in Applications Information). When V crosses the
+
–
bypass capacitor between D and D . Larger capacitors
PTAT
may cause settling time errors (see Typical Performance
threshold voltage on pin VT1 with opposite polarity, an
additional hysteresis of 20mV is required to release TO1
high after a delay adjustable by the capacitor on TMR. TO1
+
Characteristics).IfD is tied to V ,theLTC2995measures
CC
+
the internal sensor temperature. Tie D to V if unused.
CC
has a weak 400kΩ pull-up to V and may be pulled above
–
–
CC
D : Diode Sense Current Sink. Connect D to the cathode
V
CC
using an external pull-up. Leave TO1 open if unused.
–
of the remote sensor device. Tie D to GND for single
wire remote temperature measurement (see Applications
Information) or internal temperature sensing.
TO2: Temperature Logic Output 2. Open drain logic output
thatpullstoGNDwhenV crossesthethresholdvoltage
PTAT
on pin VT2 with a polarity set by the PS pin (see Table 3
in Applications Information). When V crosses the
DS: Diode Select Input. Three state pin that selects tem-
PTAT
perature sensor location. Tie DS to V to monitor the
CC
threshold voltage on pin VT2 with opposite polarity, an
additional hysteresis of 20mV is required to release TO2
high after a delay adjustable by the capacitor on TMR. TO2
temperature of the internal diode or to GND to monitor the
temperature of the external diode. When DS is left uncon-
nected, the LTC2995 monitors both sensors alternately.
has a weak 400kΩ pull-up to V and may be pulled above
+
CC
If D is tied to V , the LTC2995 measures the internal
CC
V
CC
using an external pull-up. Leave TO2 open if unused.
sensor temperature regardless of the state of DS.
UV: Undervoltage Logic Output. Open drain logic output
that pulls to GND when either the voltage at VH1 or VH2
is below 0.5V. Held low for an adjustable delay time set
by the capacitor connected to pin TMR. UV has a weak
Exposed Pad: Exposed pad may be left open or soldered
to GND for better thermal coupling.
GND: Device Ground
400kΩ pull-up to V and may be pulled above V using
CC
CC
OV: Overvoltage Logic Output. Open drain logic output
that pulls to GND when either the voltage at VL1 or VL2
is above 0.5V. Held low for a programmable delay time
set by the capacitor connected to pin TMR. OV has a weak
an external pull-up. Leave pin open if unused.
V : Supply Voltage. Bypass this pin to GND with a 0.1μF
°°
(or greater) capacitor. V operatingrangeis2.25Vto5.5V.
CC
400kΩ pull-up to V and may be pulled above V using
CC
CC
VH±, VHꢀ: Voltage High Inputs 1 and 2. When the voltage
an external pull-up. Leave OV open if unused.
on either pin is below 0.5V, an undervoltage condition is
PS: Polarity Select Input. Selects the polarity of tempera-
triggered. Tie pin to V if unused.
CC
turethresholdsVT1andVT2.ConnectPStoV toconfig-
CC
VL±, VLꢀ: Voltage Low Inputs 1 and 2. When the voltage
on either pin is above 0.5V, an overvoltage condition is
triggered. Tie pin to GND if unused.
ureVT1asundertemperatureandVT2asovertemperature
threshold. Leave PS unconnected to configure both VT1
and VT2 as overtemperature thresholds. Connect PS to
GND to configure both VT1 and VT2 as undertemperature
V
: Proportional to Absolute Temperature Voltage
PTAT
thresholds.TietoV iftemperaturethresholdsareunused.
Output. The voltage on this pin is proportional to the
CC
selected sensor’s absolute temperature. An internal or
external sensor is chosen with the DS pin. V
TMR: Reset Delay Timer. Attach an external capacitor
(CTMR) to GND to set the delay time until alerts on TO1,
TO2, UV and OV are reset. Leaving the pin open generates
a minimum delay of 500μs. Capacitance on this pin adds
can
PTAT
drive up to 200μA of load current and up to 1000pF of
capacitive load. For larger load capacitances insert a 1k
an additional 8ms/nF reset delay time. Tie TMR to V to
CC
bypass the timer.
2995f
7
Linear Systems [ Linear Systems ]
