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LTC1857IG 参数 Datasheet PDF下载

LTC1857IG图片预览
型号: LTC1857IG
PDF下载: 下载PDF文件 查看货源
内容描述: 8通道, 12位/ 14位/ 16位, 100ksps的的SoftSpan A / D转换器,带有关断 [8-Channel, 12-/14-/16-Bit, 100ksps SoftSpan A/D Converters with Shutdown]
分类和应用: 转换器光电二极管
文件页数/大小: 20 页 / 261 K
品牌: Linear Systems [ Linear Systems ]
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LTC1857/LTC1858/LTC1859  
W U  
TI I G CHARACTERISTICS  
The denotes the specifications which apply over the full operating temperature  
range, otherwise specifications are at TA = 25°C. (Note 5)  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
f
Maximum Sampling Frequency  
Through CH0 to CH7 Inputs  
Through ADC , ADC Only  
100  
kHz  
kHz  
SAMPLE(MAX)  
+
166  
4
t
t
Conversion Time  
Acquisition Time  
5
4
µs  
CONV  
ACQ  
Through CH0 to CH7 Inputs  
µs  
µs  
+
Through ADC , ADC Only  
(Note 14)  
1
f
t
t
t
t
t
t
t
t
t
SCK Frequency  
SDO Rise Time  
SDO Fall Time  
0
20  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK  
r
See Test Circuits  
See Test Circuits  
6
6
f
CONVST High Time  
CONVST to BUSY Delay  
SCK Period  
40  
1
C = 25pF, See Test Circuits  
L
15  
30  
2
50  
10  
10  
3
SCK High  
4
SCK Low  
5
Delay Time, SCKto SDO Valid  
C = 25pF, See Test Circuits  
L
25  
20  
45  
30  
6
Time from Previous SDO Data Remains C = 25pF, See Test Circuits  
Valid After SCK↓  
5
7
L
t
t
t
t
t
t
SDO Valid After RD↓  
C = 25pF, See Test Circuits  
L
11  
ns  
ns  
ns  
ns  
ns  
ns  
8
RDto SCK Setup Time  
SDI Setup Time Before SCK↑  
SDI Hold Time After SCK↑  
SDO Valid Before BUSY↑  
Bus Relinquish Time  
20  
0
9
10  
11  
12  
13  
7
RD = Low, C = 25pF, See Test Circuits  
5
20  
10  
L
See Test Circuits  
30  
Note 1: Absolute maximum ratings are those values beyond which the life  
of a device may be impaired.  
Note 2: All voltage values are with respect to ground with DGND, AGND1,  
AGND2 and AGND3 wired together unless otherwise noted.  
Note 8: Bipolar zero error is the offset voltage measured from 0.5LSB  
when the output code flickers between 0000 0000 0000 0000 and 1111  
1111 1111 1111 for the LTC1859, between 00 0000 0000 0000 and 11  
1111 1111 1111 for the LTC1858 and between 0000 0000 0000 and 1111  
1111 1111 for the LTC1857. Unipolar zero error is the offset voltage  
measured from 0.5LSB when the output codes flicker between 0000 0000  
0000 0000 and 0000 0000 0000 0001 for the LTC1859, between 00 0000  
0000 0000 and 00 0000 0000 0001 for the LTC1858 and between 0000  
0000 0000 and 0000 0000 0001 for the LTC1857.  
Note 3: When these pin voltages are taken below ground or above AV  
=
DD  
DV = OV = V , they will be clamped by internal diodes. This product  
DD  
DD  
DD  
can handle currents of greater than 100mA below ground or above V  
DD  
without latchup.  
Note 4: When these pin voltages are taken below ground they will be  
clamped by internal diodes. This product can handle currents of greater  
than 100mA below ground without latchup. These pins are not clamped  
Note 9: Guaranteed by design, not subject to test.  
Note 10: Recommended operating conditions.  
to V  
.
Note 11: Full-scale bipolar error is the worst case of –FS or +FS  
untrimmed deviation from ideal first and last code transitions, divided by  
the full-scale range, and includes the effect of offset error. For unipolar  
full-scale error, the deviation of the last code transition from ideal, divided  
by the full-scale range, and includes the effect of offset error.  
DD  
Note 5: V = 5V, f  
specified.  
Note 6: Linearity, offset and full-scale specifications apply for a single-  
ended analog MUX input with respect to ground or ADC with respect to  
= 100kHz, t = t = 5ns unless otherwise  
r f  
DD  
SAMPLE  
+
Note 12: All Specifications in dB are referred to a full-scale ±10V input.  
ADC tied to ground.  
Note 13: Recovers to specified performance after (2 • FS) input  
overvoltage.  
Note 7: Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual end points of the transfer curve.  
The deviation is measured from the center of the quantization band.  
Note 14: t of 45ns maximum allows f  
up to 10MHz for rising capture  
6
SCK  
with 50% duty cycle and f  
up to 20MHz for falling capture (with 5ns  
SCK  
setup time for the receiving logic).  
Note 15: The specification is referred to the ±10V input range.  
185789f  
5