LTC3703
applicaTions inForMaTion
Next, choose the top and bottom MOSFET switch. Since
the drain of each MOSFET will see the full supply voltage
72V (max) plus any ringing, choose a 100V MOSFET to
output voltage changes due to inductor current ripple and
load steps. The ripple voltage will be:
∆V
= ∆I
(ESR) = (4A)(0.018Ω/2)
OUT(RIPPLE)
= 36mV
L(MAX)
provide a margin of safety. Si7456DP has a 100V BV
,
DSS
R
= 25mΩ (max), δ = 0.009/°C, C
= (19nC
DS(ON)
– 10nC)/50V = 180pF, V
MILLER
= 4.7V, θ = 20°C/W.
JA
However, a 0A to 10A load step will cause an output volt-
age change of up to:
GS(MILLER)
Thepowerdissipationcanbeestimatedatmaximuminput
voltage, assuming a junction temperature of 100°C (30°C
above an ambient of 70°C):
∆V
= ∆I
= (10A)(0.009Ω) = 90mV
OUT(STEP)
LOAD(ESR)
PC Board Layout Checklist
12
72
PMAIN
=
(10)2 1+ 0.009(100–25) (0.025)
[
]
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3703.Theseitemsarealsoillustratedgraphicallyinthe
layout diagram of Figure 18. For layout of a boost mode
converter, layout is similar with V and V
Check the following in your layout:
10
2
1
1
+ (72)2
(2)(180pF)•
+
(250k)
10–4.7 4.7
= 0.70W+ 0.94W = 1.64W
swapped.
IN
OUT
And double check the assumed T in the MOSFET:
J
1. Keepthesignalandpowergroundsseparate. Thesignal
ground consists of the LTC3703 GND pin, the ground
T = 70°C + (1.64W)(20°C/W) = 103°C
J
Since the synchronous MOSFET will be conducting over
twice as long each period (almost 100% of the period
in short circuit) as the top MOSFET, use two Si7456DP
MOSFETs on the bottom:
return of C , and the (–) terminal of V . The power
VCC
OUT
groundconsistsoftheSchottkydiodeanode,thesource
of the bottom side MOSFET, and the (–) terminal of the
inputcapacitorandDRV capacitor.Connectthesignal
CC
and power grounds together at the (–) terminal of the
output capacitor. Also, try to connect the (–) terminal
of the output capacitor as close as possible to the (–)
72− 12
PSYNC
=
(10)2 1+ 0.009(100–25) •
[
]
72
0.025
2
terminals of the input and DRV capacitor and away
CC
= 1.74W
from the Schottky loop described in (2).
2.Thehighdi/dtloopformedbythetopN-channelMOSFET,
T = 70°C + (1.74W)(20°C/W) = 105°C
J
the bottom MOSFET and the C capacitor should have
IN
Next, set the current limit resistor. Since I
= 10A, the
short leads and PC trace lengths to minimize high fre-
quencynoiseandvoltagestressfrominductiveringing.
MAX
limit should be set such that the minimum current limit is
>10A.MinimumcurrentlimitoccursatmaximumR
.
DS(ON)
3. Connect the drain of the top side MOSFET directly to the
Using the above calculation for bottom MOSFET T , the
J
(+) plate of C , and connect the source of the bottom
IN
max R
= (25mΩ/2) [1 + 0.009 (105-25)] = 21.5mΩ.
DS(ON)
side MOSFET directly to the (–) terminal of C . This
IN
Therefore,I
pinvoltageshouldbesetto(10A)(0.0215)
SET
capacitor provides the AC current to the MOSFETs.
MAX
= 0.215V. The R
resistor can now be chosen to be
4. Place the ceramic C
decoupling capacitor imme-
DRVCC
0.215V/12µA = 18k.
diately next to the IC, between DRV and BGRTN. This
CC
C
(I
is chosen for an RMS current rating of about 5A
/2) at 85°C. For the output capacitor, two low ESR
capacitor carries the MOSFET drivers’ current peaks.
IN
MAX
Likewise the C capacitor should also be next to the IC
B
OS-CON capacitors (18mΩ each) are used to minimize
between BOOST and SW.
3703fc
28
Linear Systems [ Linear Systems ]
