LTC3703
applicaTions inForMaTion
GAIN
(dB)
PHASE
(DEG)
expected duty cycle (minimum V ) in order to ensure
IN
that the current limit does not kick in at loads < I
:
O(MAX)
GAIN
A
V
IO(MAX)
VPROG
=
=
RDS(ON)(1+ δ)
–12dB/OCT
1–DMAX
0
0
VOUT
IO(MAX) •RDS(ON)(1+ δ)
–90
–180
PHASE
V
IN(MIN)
Once V
is determined, R
is chosen as follows:
PROG
IMAX
R
IMAX
= V /12µA
PROG
3703 F16
Note that in a boost mode architecture, it is only possible
to provide protection for “soft” shorts where V > V .
Figure 16. Transfer Function of Boost Modulator
OUT
IN
For hard shorts, the inductor current is limited only by the
input supply capability. Refer to Current Limit Program-
ming for buck mode for further considerations for current
limit programming.
compensation component to achieve this, using a Type 1
amplifier (see Figure 12), is:
–GAIN/20
G = 10
C1 = 1/(2π • f • G • R1)
Boost Converter: Feedback Loop/Compensation
Compensating a voltage mode boost converter is unfor-
tunately more difficult than for a buck converter. This is
due to an additional right-half plane (RHP) zero that is
present in the boost converter but not in a buck. The ad-
ditional phase lag resulting from the RHP zero is difficult
if not impossible to compensate even with a Type 3 loop,
so the best approach is usually to roll off the loop gain at
a lower frequency than what could be achievable in buck
converter.
Run/Soft-Start Function
The RUN/SS pin is a multipurpose pin that provide a soft-
start function and a means to shut down the LTC3703.
Soft-start reduces the input supply’s surge current by
gradually increasing the duty cycle and can also be used
for power supply sequencing.
Pulling RUN/SS below 0.9V puts the LTC3703 into a low
quiescent current shutdown (I ≅ 50µA). This pin can be
Q
drivendirectlyfromlogicasshowninFigure17. Releasing
Atypicalgain/phaseplotofavoltagemodeboostconverter
is shown in Figure 16. The modulator gain and phase can
be measured as described for a buck converter or can be
estimated as follows:
the RUN/SS pin allows an internal 4µA current source to
RUN/SS
2V/DIV
2
GAIN (COMP-to-V
DC gain) = 20Log(V
/V )
IN
OUT
OUT
V
VOUT
1
V
OUT
IN
•
Dominant Pole: f =
5V/DIV
P
2π LC
I
L
2A/DIV
Since significant phase shift begins at frequencies above
the dominant LC pole, choose a crossover frequency no
greater than about half this pole frequency. The gain of
the compensation network should equal –GAIN at this
frequency so that the overall loop gain is 0dB here. The
3703 F17
V
= 50V
2ms/DIV
IN
I
= 2A
LOAD
C
= 0.01µF
SS
Figure 17. LTC3703 Start-Up Operation
3703fc
23
Linear Systems [ Linear Systems ]
