LTC1588/LTC1589/LTC1592
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Power Supply
V
CC
I
CC
Supply Voltage
Supply Current, V
CC
CONDITIONS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= T
MIN
to T
MAX
, V
CC
= 5V, V
REF
= 5V, I
OUT2
= AGND = GND = 0V.
MIN
q
TYP
5
MAX
5.5
10
UNITS
V
µA
4.5
Digital Inputs = 0V or V
CC
q
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
±1LSB
=
±0.0015%
of full scale =
±15.3ppm
of full scale
(LTC1592).
±1LSB
=
±0.006%
of full scale =
±61.2ppm
of full scale
(LTC1589).
±1LSB
= 0.024% of full scale =
±244.8ppm
of full scale
(LTC1588).
Note 3:
Using internal feedback resistor.
Note 4:
Guaranteed by design, not subject to test.
Note 5:
I
OUT1
with DAC register loaded to all 0s.
Note 6:
Typical temperature coefficient is 100ppm/°C.
Note 7:
To 0.0015% for a full-scale change, measured from the falling
edge of LD for the LTC1592 only.
Note 8:
REF = 6V
RMS
at 1kHz. DAC register loaded with all 1s. Output
amplifier = LT1468.
Note 9:
Calculation from e
n
=
√4kTRB
where: k = Boltzmann constant
(1.38E-23 J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth
(Hz).
Note 10:
Midscale transition code: 32767 to 32768 for the LTC1592, 8191
to 8192 for the LTC1589, 2047 to 2048 for the LTC1588.
Note 11:
R1 and R2 are measured between R1 and R
COM
, R2 and R
COM
.
Note 12:
If a continuous clock is used with data changing on the rising
edge of SCK, setup and hold time (t
1
, t
2
) will limit the maximum clock
frequency. If data changes on the falling edge of SCK then the setup time
will limit the maximum clock frequency to 8MHz (continuous 50% duty
cycle clock).
Note 13:
SDO propagation delay and SDI setup time (t
8
, t
1
) limit the
maximum clock frequency for daisy chaining.
TYPICAL PERFOR A CE CHARACTERISTICS
(LTC1588/LTC1589/LTC1592)
Midscale Glitch Impulse
40
30
USING AN LT1468
C
FEEDBACK
= 30pF
V
REF
= 10V
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (mV)
LOGIC THRESHOLD (V)
20
10
0
–10
–20
– 30
– 40
1nV-s TYPICAL
0
0.2
0.4
0.6
TIME (µs)
4
U W
0.8
1588992 G03
Supply Current vs Input Voltage
5
Logic Threshold vs Supply Voltage
3.0
4
V
CC
= 5V
ALL DIGITAL INPUTS
TIED TOGETHER
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
1.0
0
1
3
2
INPUT VOLTAGE (V)
4
5
1588992 G09
0
1
5
2
3
4
SUPPLY VOLTAGE (V)
6
7
1588992 G10
1588992fa
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
