LTC1588/LTC1589/LTC1592
U
U
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PI FU CTIO S
IOUT1 (Pin 5): True DAC Current Output. Tied to the
inverting input of the current-to-voltage op amp.
SCK (Pin 12): Serial Interface Clock. Data on the SDI pin
isshiftedintotheinputshiftregisteronrisingedgeofSCK.
IOUT2 (Pin 6): Complement of DAC Current Output. Nor-
CS/LD (Pin 13): Chip Select Input. When CS/LD is low,
SCKisenabledforshiftingdataintotheinputshiftregister.
WhenCS/LDispulledhigh,SCKisdisabledandthecontrol
logic executes the control word (the first 4 bits of the input
data stream as shown in Table 1).
mally tied to AGND pin.
AGND (Pin 7): Analog Ground. Tie to the system’s analog
ground plane.
GND (Pin 8): Ground. Tie to the system’s analog ground
plane.
CLR (Pin 14): When CLR is taken to a logic low, it sets the
DAC output to 0V and all internal registers to zero code.
VCC (Pin 9): Positive Supply Input. 4.5V ≤ VCC ≥ 5.5V.
Requires a 0.1µF bypass capacitor to ground.
REF (Pin 15): DAC Reference Input. Typically 5V, accepts
up to ±15V.
SDO(Pin10): SerialDataOutput. Dataatthispinisshifted
out on the rising edge of SCK.
R2 (Pin 16): Bipolar Resistor R2. Normally tied to the DAC
referenceinputREF(Pin15)andtheoutputoftheinverting
amplifier tied to RCOM (Pin 1).
SDI (Pin 11): Serial Data Input.
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FU CTIO TABLE
Table 1
Internal Register Status
SREG
DATA WORD
Dn IN INPUT
BUF1
BUF2
DAC
BUFFER
(DAC OUTPUT)
No Change
Dn
COMMAND
OPERATION
EACH COMMAND IS EXECUTED
ON THE RISING EDGE OF CS/LD
DAC
OUTPUT
RANGE
No Change
No Change
No Change
INPUT
C3 C2 C1 C0
SHIFT REGISTER BUFFER
Dn
X
Dn
Dn
Dn
Dn
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Copy Data Word Dn in SReg to Buf1
Copy the Data in Buf1 to Buf2
Copy Data Word Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Reserved (Do Not Use)
Set Range to 5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to 10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±10V. Copy Dn in SReg to Buf1 and Buf2
Set Range to ±2.5V. Copy Dn in SReg to Buf1 and Buf2
Set Range to –2.5V to 7V. Copy Dn in SReg to Buf1 and Buf2
Reserved (Do Not Use)
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
Dn
5V
10V
±5V
±10V
±2.5V
–2.5V to 7.5V
X
No Change No Change
No Change
No Operation
Data Word Dn (n = 0 to 15) is the last 16 bits shifted into the input shift register SReg that corresponds to the DAC code.
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Linear Systems [ Linear Systems ]
