LTC1588/LTC1589/LTC1592
U
OPERATIO
INPUT WORD (LTC1588)
COMMAND
DON’T CARE
DATA (12 BITS + 4 DON’T-CARE BITS)
X
X
X
D6
D5 D4 D3 D2 D1
D0
X
X
X
X
X
C3
C1
X
D11 D10 D9 D8
MSB
D7
C2
C0
1588992 TD4
LSB
INPUT WORD (LTC1589)
COMMAND
DON’T CARE
DATA (14 BITS + 2 DON’T-CARE BITS)
X
X
X
X
X
D12
D6
D0
X
C3
C1
X
D13
D11 D10 D9 D8
D5 D4 D3 D2 D1
D7
C2
C0
C0
1588992 TD3
MSB
LSB
INPUT WORD (LTC1592)
COMMAND
DON’T CARE
DATA (16 BITS)
D6
D5 D4 D3 D2 D1
X
D12
D0
C3
C1
X
D15 D14 D13
MSB
D11 D10 D9 D8
D7
C2
LSB
1588992 TD2
Serial Interface
clocked to all ICs, then the CS/LD signal is pulled high to
update all of them simultaneously.
When the CS/LD is brought to a logic low, the data on the
SDIinputisloadedintotheshiftregisterontherisingedge
of the clock. A 4-bit command word (C3 C2 C1 C0),
followed by four “don’t care” bits and 16 data bits
(MSB-first)istheminimumloadingsequencerequiredfor
the LTC1588/LTC1589/LTC1592. When the CS/LD is
brought to a logic high, the clock is disabled internally and
the command word is executed.
Power-On Reset and Clear
When the power supply is first turned on, the LTC1588/
LTC1589/LTC1592 will power up in 5V unipolar mode (C3
C2 C1 C0 = 1000). All the internal registers are set to zeros
and the DAC is set to zero code.
The LTC1588/LTC1589/LTC1592 must first be pro-
grammed in either unipolar or bipolar mode. There are six
operating modes available and can be software-pro-
grammed by the command word. When a CLR signal is
brought to low, it clears all internal registers to zero. The
DAC output voltage goes to zero volts. If an update DAC
command (C3 C2 C1 C0 = 0001) is issued immediately
after the CLR signal, the DAC output remains at zero volts.
If no daisy-chaining is required, the input stream can be
24-bitwideasshowninFigure1a.Thefirstfourbitsarethe
command word, followed by four “don’t care” bits, then a
16-bit data word. The last four bits (LSBs) of this 16-bit
data word are don’t cares for the LTC1588. For the
LTC1589, the last 2 bits of the 16-bit data word are don’t
cares.
IfaCLRsignalisgivenwithina100nsintervalimmediately
after CS/LD goes high, the user should reload the output
range.
If daisy-chaining is required or the input needs to be
writtenintwo16-bitwidesegments, thentheinputstream
must be 32-bit wide and the first 8 bits loaded are “don’t
care” bits. The remaining bits work the same as a 24-bit
stream which is described in the previous paragraph. The
outputoftheinternal32-bitshiftregisterisavailableonthe
SDO pin 32 clock cycles later.
Output Range Programming
There are two output ranges available in unipolar mode
and four output ranges available in bipolar mode. See
Function Table for details. All output ranges are with re-
specttoa5Vreferenceinput.WhenchangingtheLTC1588/
LTC1589/LTC1592 to a new mode, the command word
and data are given at the same time (24 or 32 bit). When
Multiple LTC1588/LTC1589/LTC1592s may be daisy-
chained together by connecting the SDOpin to the SDI pin
of the next IC. The clock and CS/LD signals should remain
common to all ICs in the daisy-chain. The serial data is
1588992fa
9
Linear Systems [ Linear Systems ]
