LTC1174
LTC1174-3.3/LTC1174-5
U
W U U
APPLICATIO S I FOR ATIO
Board Layout Checklist
DESIGN EXAMPLE
As a design example, assume VIN = 9V (nominal), VOUT
5V, and IOUT = 350mA maximum. The LTC1174-5 is used
forthisapplication,withIPGM (Pin7)connectedtoVIN.The
minmum value of L is determined by assuming the
LTC1174-5 is operating in continuous mode.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1174. These items are also illustrated graphically in
the layout diagram in Figure 7. Check the following in your
layout:
=
1. Is the Schottky catch diode closely connected between
ground (Pin 4) and switch (Pin 5)?
I
PEAK
= I
OUT
AVG CURRENT
2. Is the “+” plate of CIN closely connected to VIN (Pin 6)?
This capacitor provides the AC current to the internal
P-channel MOSFET.
I
+ I
V
PEAK
2
=
I
V
= 350mA
3. Is the 0.1µF VIN decoupling capacitor closely conected
between VIN (Pin 6) and ground (Pin 4)? This capacitor
carries the high frequency peak currents.
TIME
1174 F08
Figure 8. Continuous Inductor Current
4. Is the SHUTDOWN (Pin 8) actively pulled to VIN during
normal operation? The SHUTDOWN pin is high imped-
ance and must not be allowed to float.
With IOUT = 350mA and IPEAK = 0.6A (IPGM = VIN), IV =
0.1A.The peak-to-peak ripple inductor current, IRIPPLE, is
0.5A and is also equal to:
5. Is the IPGM (Pin 7) pulled either to VIN or ground? The
IPGM pin is high impedance and must not be allowed
to float.
V
+ VD
⎛
⎜
⎝
⎞
⎟
⎠
OUT
IRIPPLE = 4 •10−6
A
P−P
(
)
L
8
1
2
3
V
OUT
FB
SHUTDOWN
(V
)
7
6
LB
LB
I
OUT
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
PGM
R1
R2
V
V
V
IN
IN
IN
LTC1174
+
0.1µF
VERSION ONLY
C
IN
4
5
SW
GND
D
L
BOLD LINES INDICATE
HIGH CURRENT PATH
C
OUT
+
OUT
1174 F07
Figure 7. LTC1174 Layout Diagram (See Board Layout Checklist)
1174fe
11
Linear Systems [ Linear Systems ]
