LTC3109
ELECTRICAL CHARACTERISTICS
board layout, the rated thermal package thermal resistance and other
ꢁote 5: Failure to solder the exposed backside of the QFN package to the
PC board ground plane will result in a thermal resistance much higher
than 37°C/W.
environmental factors. The junction temperature (T ) is calculated from
J
the ambient temperature (T ) and power dissipation (P ) according to
A
D
the formula: T = T + (P • θ °C/W), where θ is the package thermal
impedance.
ꢁote ±: Specification is guaranteed by design and not 100% tested in
production.
J
A
D
JA
JA
ꢁote 6: The Absolute Maximum Rating is a DC rating. Under certain
conditions in the applications shown, the peak AC voltage on the C2A and
C2B pins may exceed 8V. This behavior is normal and acceptable because
the current into the pin is limited by the impedance of the coupling
capacitor.
ꢁote 4: Current measurements are made when the output is not switching.
TYPICAL PERFORMANCE CHARACTERISTICS Tꢃ = 251C, unless otherwise noteꢂ.
IIꢁ vs VIꢁ
IVOUT vs VIꢁ
PVOUT vs VIꢁ
10000
1000
100
100
10
1
1000
100
10
V
= 0V
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
1:50 RATIO
C1 = 4.7nF
OUT
V
= 3.3V
OUT
V
= 5V
OUT
NO LOAD ON VLDO
V
OUT
= 3.3V
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
10
0.1
1
10
100
(mV)
1000
10
100
V (mV)
IN
1000
10
100
(mV)
1000
V
V
IN
IN
3109 G02
3109 G18
3109 G01
Open-CirAuit Start-Up Voltage
vs SourAe ResistanAe
Input ResistanAe vs VIꢁ
EffiAienAy vs VIꢁ
50
45
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
V
= 0V
OUT
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
V
= 0V
OUT
1:100 RATIO, C1 = 1nF
1:50 RATIO, C1 = 4.7nF
1:20 RATIO, C1 = 10nF
0
10
100
(mV)
1000
10
100
1000
0
1
2
3
4
5
10
6
7
8
9
V
V
(mV)
SOURCE RESISTANCE (Ω)
IN
IN
3109 G04
3109 G03
3109 G05
3109fa
4
Linear Systems [ Linear Systems ]
