LT3467/LT3467A
APPLICATIONS INFORMATION
LOAD CURRENT
100mA/DIV
AC COUPLED
Layout Hints
ThehighspeedoperationoftheLT3467/LT3467Ademands
careful attention to board layout. You will not get adver-
tised performance with careless layout. Figure 5a shows
the recommended component placement for the ThinSOT
package. Figure 5b shows the recommended component
placement for the DFN package. Note the vias under the
Exposed Pad. These should connect to a local ground
plane for better thermal performance.
V
OUT
200mV/DIV
AC COUPLED
I
L1
5A/DIV
AC COUPLED
3467 F03
20μs/DIV
Figure 3. Transient Response of Figure 8’s Step-Up
Converter without Phase Lead Capacitor
L1
D1
C1
V
IN
V
OUT
LOAD CURRENT
C2
1
2
3
6
5
4
100mA/DIV
C
SS
AC COUPLED
SS
GND
SHDN
V
OUT
FB
200mV/DIV
R2
R1
AC COUPLED
I
L1
3467 F05a
5A/DIV
C3
V
OUT
AC COUPLED
3467 F04
20μs/DIV
Figure 5a. Suggested Layout—ThinSOT
Figure 4. Transient Response of Figure 8’s Step-Up
Converter with a 22pF Phase Lead Capacitor
V
OUT
C3
R1
Setting Output Voltage
R2
To set the output voltage, select the values of R1 and R2
(see Figure 2) according to the following equation.
SHDN
FB
1
2
3
4
8
7
6
5
GND
C
SS
VOUT
⎛
⎞
R1=R2
–1
C2
⎜
⎝
⎟
⎠
1.255V
V
OUT
V
IN
D1
A good value for R2 is 13.3k which sets the current in the
resistor divider chain to 1.255V/13.3k = 94μA.
C1
L1
3467 F05b
Figure 5b. Suggested Layout—DFN
3467afe
9
Linear Systems [ Linear Systems ]
