LTC3261
APPLICATIONS INFORMATION
should be consulted to ensure the desired capacitance at
all temperatures and voltages. Table 1 is a list of ceramic
capacitor manufacturers and their websites.
Table 1
AVX
Kemet
Murata
Taiyo Yuden
Vishay
TDK
www.avxcorp.com
www.kemet.com
www.murata.com
www.t-yuden.com
www.vishay.com
www.component.tdk.com
The power dissipated in the LTC3261 is:
P
D
= (V
IN
– |V
OUT
|) • (I
OUT
)
where I
OUT
denotes output current at the V
OUT
pin.
The derating curve in Figure 4 assumes a maximum thermal
resistance,
θ
JA
, of 40°C/W for the package. This can be
achieved from a printed circuit board layout with a solid
ground plane and a good connection to the exposed pad
of the LTC3261 package.
It is recommended that the LTC3261 be operated in the
region corresponding to T
J
≤ 150°C for continuous opera-
tion as shown in Figure 4. Short-term operation may be
acceptable for 150°C < T
J
< 175°C but long-term operation
in this region should be avoided as it may reduce the life of
the part or cause degraded performance. For T
J
> 175°C
the part will be in thermal shutdown.
GND
C
FLY
Layout Considerations
Due to high switching frequency and high transient currents
produced by LTC3261, careful board layout is necessary
for optimum performance. A true ground plane and short
connections to all the external capacitors will improve
performance and ensure proper regulation under all condi-
tions. Figure 3 shows an example layout for the LTC3261.
The flying capacitor nodes C
+
and C
–
switch large currents
at a high frequency. These nodes should not be routed
close to sensitive pins such as the RT pin .
V
IN
V
OUT
Thermal Management
At high input voltages and maximum output current, there
can be substantial power dissipation in the LTC3261. If
the junction temperature increases above approximately
175°C, the thermal shutdown circuitry will automatically
deactivate the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board
ground plane is recommended. Connecting the exposed pad
of the package to a ground plane under the device on two
layers of the PC board can reduce the thermal resistance
of the package and PC board considerably.
Derating Power at High Temperatures
To prevent an overtemperature condition in high power
applications, Figure 4 should be used to determine the
maximum combination of ambient temperature and power
dissipation.
The power dissipated in the LTC3261 should always fall
under the line shown for a given ambient temperature.
EN
MODE
GND
R
T
3261 F03
Figure 3. Recommended Layout
6
MAXIMUM POWER DISSIPATION (W)
5
4
T
J
= 175°C
3
2
1
0
–50 –25
RECOMMENDED
OPERATION
T
J
= 150°C
θ
JA
= 40°C/W
THERMAL
SHUTDOWN
0 25 50 75 100 125 150 175
AMBIENT TEMPERATURE (°C)
3261 F04
Figure 4. Maximum Power Dissipation vs Ambient Temperature
3261f
9
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
