Figure 1. Operational Amplifier Protection
Input Differential Voltage limited to 0.8V (typ) by JPADs D
1
and D
2
. Common
Mode Input voltage limited by JPADs D
3
and D
4
to ±15V.
Figure 2. Sample and Hold Circuit
Typical Sample and Hold circuit with clipping. JPAD diodes reduce offset
voltages fed capacitively from the JFET switch gate.
FIGURE 1
FIGURE 2
+V
JPAD20
D1
D3
D2
D4
-
OP-27
+
-V
D2
+V
JPAD5
D1
2N4117A
2N4393
C
e
in
+15V -15V
CONTROL
SIGNAL
R
V
OUT
TO-72
Three Lead
0.195 DIA.
0.175
0.030
MAX.
0.230
DIA.
0.209
0.150
0.115
0.170
0.195
0.175
0.195
TO-92
0.130
0.155
0.045
0.060
0.89
1.03
SOT-23
1
1.78
2.05
0.37
0.51
LS XXX
YYWW
3
2
1.20
1.40
2.10
2.64
0.085
0.180
2.80
3.04
3 LEADS
0.019 DIA.
0.016
0.100
0.500 MIN.
0.016
0.022
0.500
0.610
0.014
0.020
0.89
1.12
0.050
0.013
0.100
1
2
0.55
DIMENSIONS IN
MILLIMETERS
1
2
3
0.095
0.105
DIMENSIONS
IN INCHES.
45°
0.046
0.036
0.048
0.028
1.
2.
Absolute maximum ratings are limiting values above which serviceability may be impaired.
The PAD type number denotes its maximum reverse current value in pico amperes. Devices with I
R
values intermediate to those shown
are available upon request.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems
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