Data Sheet
Austin MiniLynxTM SIP Non-isolated Power Modules:
February 26, 2009
2.4 – 5.5Vdc input; 0.75Vdc to 3.63Vdc Output; 3A output current
Test Configurations
Design Considerations
Input Filtering
CURRENT PROBE
TO OSCILLOSCOPE
The Austin MiniLynxTM SIP module should be connected
to a low-impedance source. A highly inductive source
LTEST
VIN(+)
1μH
can affect the stability of the module. An input
capacitance must be placed directly adjacent to the
input pin of the module, to minimize input ripple voltage
and ensure module stability.
CIN
CS 1000μF
Electrolytic
2x100μF
Tantalum
E.S.R.<0.1Ω
To minimize input voltage ripple, low-ESR polymer and
@ 20°C 100kHz
ceramic capacitors are recommended at the input of the
COM
module. Figure 28 shows the input ripple voltage
(mVp-p) for various outputs with 1x22µF (TDK:
NOTE: Measure input reflected ripple current with a simulated
source inductance (LTEST) of 1μH. Capacitor CS offsets
possible battery impedance. Measure current as shown
above.
C3225X5R0J226V) ceramic capacitor at the input of the
module. Figure 29 shows the input ripple with 1x47µF
(TDK: C3225X5R0J476M) ceramic capacitor at full load.
Figure 25. Input Reflected Ripple Current Test
Setup.
160
3.3Vin
140
COPPER STRIP
5Vin
120
100
80
60
40
20
0
VO(+)
COM
RESISTIVE
LOAD
1uF
.
10uF
SCOPE
GROUND PLANE
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
Figure 26. Output Ripple and Noise Test Setup.
0
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (Vdc)
Rdistribution Rcontact
Rcontact Rdistribution
Figure 28. Input ripple voltage for various outputs
with 1x22 µF ceramic capacitor at the input (full-
load).
VIN(+)
VO
16 0
RLOAD
VO
VIN
3.3Vin
14 0
5Vin
Rdistribution Rcontact
Rcontact Rdistribution
12 0
10 0
80
60
40
20
0
COM
COM
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
Figure 27. Output Voltage and Efficiency Test Setup.
VO. IO
Efficiency
=
x
100 %
η
0
0.5
1
1.5
2
2.5
3
3.5
VIN. IIN
Output Voltage (Vdc)
Figure 29. Input ripple voltage for various outputs
with 1x47 µF ceramic capacitor at the input (full
load).
LINEAGE POWER
10
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
