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ATS020A0X3-SRH 参数 Datasheet PDF下载

ATS020A0X3-SRH图片预览
型号: ATS020A0X3-SRH
PDF下载: 下载PDF文件 查看货源
内容描述: 4.5 - 5.5V直流输入; 0.8〜 3.63Vdc输出; 30A的输出电流, 6.0 - 14VDC输入; 0.8Vdc到3.63Vdc输出; 20 / 30A输出 [4.5 - 5.5Vdc input; 0.8 to 3.63Vdc Output; 30A output current, 6.0 - 14Vdc Input; 0.8Vdc to 3.63Vdc Output; 20/30A output]
分类和应用:
文件页数/大小: 28 页 / 1039 K
品牌: LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
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Data Sheet  
Austin MegaLynxTM SMT: Non-Isolated DC-DC Power Modules:  
4.5 – 5.5Vdc input; 0.8 to 3.63Vdc Output; 30A output current  
6.0 – 14Vdc Input; 0.8Vdc to 3.63Vdc Output; 20/30A output  
June 3, 2009  
Test Configurations  
Design Considerations  
The Austin MegaLynxTM module should be  
connected to a low-impedance source. A highly  
inductive source can affect the stability of the  
CURRENT PROBE  
TO OSCILLOSCOPE  
module. An input capacitor must be placed directly  
adjacent to the input pin of the module, to minimize  
LTEST  
VIN(+)  
1μH  
input ripple voltage and ensure module stability.  
CIN  
Min  
To minimize input voltage ripple, low-ESR ceramic  
capacitors are recommended at the input of the  
module. Figure 46 shows the input ripple voltage for  
CS 220μF  
E.S.R.<0.1Ω  
150μF  
@ 20°C 100kHz  
various output voltages at 30A of load current with  
COM  
1x22 µF or 2x22 µF ceramic capacitors and an  
input of 12V. Figure 47 shows data for the 5Vin  
case, with 2x22µF and 2x47µF of ceramic  
capacitors at the input, and for a load current of  
30A.  
NOTE: Measure input reflected ripple current with a simulated  
source inductance (LTEST) of 1μH. Capacitor CS offsets  
possible battery impedance. Measure current as shown  
above.  
350  
Figure 43. Input Reflected Ripple Current Test  
Setup.  
1 x 22uF  
300  
2 x 22uF  
250  
COPPER STRIP  
200  
150  
100  
50  
VO(+)  
COM  
RESISTIVE  
LOAD  
1uF  
.
10uF  
SCOPE  
GROUND PLANE  
0
NOTE: All voltage measurements to be taken at the module  
terminals, as shown above. If sockets are used then  
Kelvin connections are required at the module terminals  
to avoid measurement errors due to socket contact  
resistance.  
0.5  
1
1.5  
2
2.5  
Output Voltage (Vdc)  
Figure 46. Input ripple voltage for various  
output voltages with 1x22 µF or 2x22 µF ceramic  
capacitors at the input (30A load). Input voltage  
is 12V.  
Figure 44. Output Ripple and Noise Test Setup.  
Rdistribution Rcontact  
Rcontact Rdistribution  
VIN(+)  
VO  
120  
100  
80  
RLOAD  
VO  
VIN  
Rdistribution Rcontact  
Rcontact Rdistribution  
60  
COM  
COM  
40  
NOTE: All voltage measurements to be taken at the module  
terminals, as shown above. If sockets are used then  
Kelvin connections are required at the module terminals  
to avoid measurement errors due to socket contact  
resistance.  
2 x 22uF  
20  
2 x 47uF  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
Figure 45. Output Voltage and Efficiency Test  
Setup.  
Output Voltage (Vdc)  
Figure 47. Input ripple voltage in mV, p-p for  
various output voltages with 2x22 µF or 2x47 µF  
ceramic capacitors at the input (30A load). Input  
voltage is 5V.  
VO. IO  
Efficiency  
=
x
100 %  
η
VIN. IIN  
LINEAGE POWER  
14  
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