Data Sheet
Austin MicroLynxTM II SIP Non-isolated Power Modules:
June 24, 2008
2.4 – 5.5Vdc input; 0.75Vdc to 3.63Vdc Output; 6A output current
Test Configurations
Design Considerations
Input Filtering
CURRENT PROBE
TO OSCILLOSCOPE
The Austin MicroLynxTM II SIP module should be
connected to a low-impedance source. A highly
LTEST
VIN(+)
1μH
inductive source can affect the stability of the module.
An input capacitance must be placed directly adjacent
to the input pin of the module, to minimize input ripple
voltage and ensure module stability.
CIN
CS 1000μF
Electrolytic
2x100μF
Tantalum
E.S.R.<0.1Ω
@ 20°C 100kHz
To minimize input voltage ripple, low-ESR polymer
COM
and ceramic capacitors are recommended at the input
of the module. Figure 26 shows the input ripple
NOTE: Measure input reflected ripple current with a simulated
source inductance (LTEST) of 1μH. Capacitor CS offsets
possible battery impedance. Measure current as shown
above.
voltage (mVp-p) for various outputs with 1x150 µF
polymer capacitors (Panasonic p/n: EEFUE0J151R,
Sanyo p/n: 6TPE150M) in parallel with 1 x 47 µF
ceramic capacitor (Panasonic p/n: ECJ-5YB0J476M,
Taiyo- Yuden p/n: CEJMK432BJ476MMT) at full load.
Figure 27 shows the input ripple with 2x150 µF
polymer capacitors in parallel with 2 x 47 µF ceramic
capacitor at full load.
Figure 23. Input Reflected Ripple Current Test Setup.
COPPER STRIP
VO(+)
COM
RESISTIVE
LOAD
12 0
10 0
80
1uF
.
10uF
SCOPE
GROUND PLANE
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
60
40
Vin = 3.3V
20
Figure 24. Output Ripple and Noise Test Setup.
Vin =5.0V
0
Rdistribution Rcontact
Rcontact Rdistribution
0
1
2
3
4
VIN(+)
VO
Output Voltage (Vdc)
Figure 26. Input ripple voltage for various output
with 1x150 µF polymer and 1x47 µF ceramic
capacitors at the input (80% of Io,max).
RLOAD
VO
VIN
Rdistribution Rcontact
Rcontact Rdistribution
12 0
10 0
80
COM
COM
NOTE: All voltage measurements to be taken at the module
terminals, as shown above. If sockets are used then
Kelvin connections are required at the module terminals
to avoid measurement errors due to socket contact
resistance.
60
Figure 25. Output Voltage and Efficiency Test Setup.
40
Vin =3.3V
20
VO. IO
Vin = 5.0V
0
Efficiency
=
x
100 %
η
VIN. IIN
0
1
2
3
4
Output Voltage (Vdc)
Figure 27. Input ripple voltage for various output
with 2x150 µF polymer and 2x47 µF ceramic
capacitors at the input (80% of Io,max).
LINEAGE POWER
10
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
