Application Guidelines for Non-Isolated Converters
AN04-006: PWB Layout Considerations
Application Note
October 22, 2008
output/ground pins as possible to provide the most
effective output filtering. Similarly on the input side,
interconnect inductance is minimized by placing the V
IN
and ground planes close together and the input
capacitors are placed as close to the input/pins as
possible.
prevent any coupling. The ground plane can be placed
under the module. For repair and removal of the SMT
module from the PWB, 4.0 mm (0.16 inches) of
clearance is recommended around the module outline.
This clearance provides clearance and isolates adjacent
components from exposure to heat during the removal
process.
Sizing Traces and Vias
Whenever possible, copper planes should be used for
routing power traces (input, output and ground
connections. In most applications, the application PWB
will have multiple layers with the top and bottom layers
being primarily used for routing signals. This leads to the
inner layers being used for ground, input and output.
With non-isolated modules, since the input voltage is
often used to feed multiple modules, one layer can be
assigned to it. The output can either be another layer or
part of a layer. In applications where the layout is very
tight, input and output may only be portions of inner
layers. When inner layers are used with SMT modules,
multiple vias are needed to carry the current from the top
layer to the inner power planes. A rule of thumb is to
have 3A/per via. The recommended via size is 22 mils
(0.022” or 560µm) plated-through hole. For control pins,
one via per pin is sufficient. Vias should be located in the
direction of current flow (location of the load ICs – See
recommended layouts for load and source arrows) for
optimum performance. For signal traces, the
recommended trace width for signal traces is 7 – 10 mils
(180 - 250µm). For bulk capacitors, 1-2 vias per
capacitor connection are recommended. Figure 3 shows
a layout of the Austin Lynx module showing vias located
near the output, input and ground pins for carrying
current to the inner layers.
Dual Layout for Lynx and MicroLynx Series
In applications where there is uncertainty on the required
load current levels, it may be useful to have a Lynx and
MicroLynx module both laid out together. Such an
arrangement allows for the lower-current MicroLynx to be
used in the event that actual load currents move lower as
the design progresses. Figure 4 shows such an example
dual layout, where the Lynx module outline and pin
locations are shown in black and the MicroLynx in blue.
Example Layouts for SIP Modules
Figures 5 shows an example layout for the Austin Lynx
and SuperLynx series SIP modules, and Fig. 6 shows
the example layout for the Austin MicroLynx series SIP
modules. Both layouts follow the same guidelines of
having the ground layer extend below the modules and
placing input and output capacitors as close as possible
to the input/ground and output/ground pins. Thermal
reliefs should be used with holes associated with
through-hole pins connected to large planes as per the
guidelines in IPC 2222, section 9.1.2.
To Load
V
OUT
PLANE
C
OUT
SENSE
VOUT
TRIM
TRIM
GND
VOUT
GND
External Component Placement
Austin Lynx dc-dc module should be placed to minimized
loop area and noise coupling. Signal traces should not
be routed underneath the module, unless sandwiched
between ground planes, to avoid noise coupling. Also,
components should not be placed under the module to
To Load
V
OUT
PLANE
C
OUT
ON/OFF
ON/OFF
SENSE
TRIM
VOUT
GND
GROUND
PLANE
VIN
VIN
GROUND
PLANE
ON/OFF
VIN
C
IN
V
IN
PLANE
To Source
C
IN
V
IN
PLANE
Fig. 4. Example showing dual layout of Austin Lynx and
MicroLynx series modules.
To Source
Fig. 3. Austin Lynx II and SuperLynx II SMT recommended
layout showing placement of vias.
LINEAGE
POWER
2
LINEAGEPOWER [ LINEAGE POWER CORPORATION ]
