LC470EUF
Product Specification
# APPENDIX- III-2
■ Required signal assignment for Flat Link (Thine : THC63LVD103) Transmitter(Pin7=“H”)
Host System
30 Bit
THC63LVD103
or Compatible
Timing
Controller
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
RED8
4
5
FI-RE51S-HF
59
61
33
34
35
36
37
38
6
31
30
TA-
12
13
RO0N
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
TA+
RO0P
29
28
TB-
14
15
RO1N
RO1P
TB+
RED9
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
GREEN8
GREEN9
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
BLUE8
BLUE9
Hsync
25
24
TC-
16
17
RO2N
RO2P
8
62
63
40
41
42
44
45
46
9
TC+
23
22
TCLK-
TCLK+
19
20
ROCLKN
ROCLKP
21
20
TD-
22
23
RO3N
RO3P
TD+
11
64
1
19
18
TE-
24
25
RO4N
RO4P
TE+
48
49
50
52
53
54
55
57
58
12
7
VESA /JEIDA
LCM Module
Vsync
Data Enable
CLOCK
Note :1. The LCD module uses a 100 Ohm[Ω] resistor between positive and negative lines of each receiver
input.
2. Refer to LVDS Transmitter Data Sheet for detail descriptions. (THC63LVD103 or Compatible)
3. ‘9’ means MSB and ‘0’ means LSB at R,G,B pixel data.
33 /40
Ver. 1.5
LG [ LG SEMICON CO.,LTD. ]
