POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
wide range of ways VCC can rise to its steady state, two
conditions are required to insure a valid power-up reset.
These conditions are:
1. The VCC rise must be monotonic.
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Max
Unit
tPR
tS
10
µs
See
Switching
Characteristics
tWL
VCC
4 V
Power
tPR
Registered
Output
tS
Clock
tWL
16751E-31
Power-Up Reset Waveform
28
MACH215-12/15/20
LATTICE [ LATTICE SEMICONDUCTOR ]
