0 1
1 1
Output Enable
Product Terms
(Common to bank of
I/O Cells)
1 0
0 0
V
CC
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
14051K-007
Figure 7. I/O Cell
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
MACH 1 & 2 SpeedLocking
Non-MACH
• Variable
• Patented Architecture
• Path Dependent
• Path Independent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
SpeedLocking
Shared Expander Delay
10.4 ns
Non-MACH
11
10
9
8.8 ns
t
(ns)
PD
8
7
6
5
Parallel Expander Delay
7.4 ns
6.6 ns
5.8 ns
5 ns
MACH 1 & 2
5 PT
10 PT
15 PT
14051K-001
Product Terms
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
12
MACH 1 & 2 Families
LATTICE [ LATTICE SEMICONDUCTOR ]
