44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin PLCC
40
1 44 43 42 41
6
5
4
3
2
I/O27
39
7
8
I/O5
38
I/O26
I/O6
I/O25
37
36
35
34
I/O7
(TDI) I0
9
I/O24
10
11
12
CLK3/I5 (TDO)
GND
(CLK 0/I0) CLK0/I1
GND
Block B
Block A
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
33
32
31
30
29
(TCK) CLK1/I2
I/O8
13
14
15
16
17
I/O9
I/O22
I/O10
I/O21
I/O11
28
18 19 20 21 22 23 24 25 26 27
14051K-018
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
MACH 1 & 2 Families
35
LATTICE [ LATTICE SEMICONDUCTOR ]
