Pinout Information
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP
LFEC1
LFEC3
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
GND0
GND0
-
1*
-
GND7
VCCIO7
PL2A
PL2B
NC
GND7
2
7
7
7
-
VCCIO7
PL2A
PL2B
NC
7
7
7
-
3
T
VREF2_7
VREF1_7
T
VREF2_7
VREF1_7
4
C
C
5
6
NC
-
NC
-
7
NC
-
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
VCCIO7
PL6B
PL7A
PL7B
PL8A
NC
7
7
7
7
7
7
7
7
7
7
7
-
8
NC
-
T
C
T
C
T
9
NC
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
-
NC
-
NC
-
LDQS6
NC
-
NC
-
C
T
C
T
PL3A
PL3B
PL4A
NC
7
7
7
-
T
C
T
PL4B
PL5A
PL5B
NC
7
7
7
-
C
T
PL8B
PL9A
PL9B
VCCAUX
XRES
NC
7
7
7
-
C
T
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
C
C
XRES
NC
6
-
6
-
NC
-
NC
-
VCC
TCK
GND
TDI
-
VCC
-
6
-
TCK
6
-
GND
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TDO
VCCJ
PL7A
PL7B
PL8A
PL8B
VCCIO6
PL9A
PL9B
PL10A
GND6
PL10B
TMS
TDO
VCCJ
PL11A
PL11B
PL12A
PL12B
VCCIO6
PL13A
PL13B
PL14A
GND6
PL14B
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
C
T
C
T
T
C
T
C
C
4-14
LATTICE [ LATTICE SEMICONDUCTOR ]
