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ISPLSI5256VA-100LB272 参数 Datasheet PDF下载

ISPLSI5256VA-100LB272图片预览
型号: ISPLSI5256VA-100LB272
PDF下载: 下载PDF文件 查看货源
内容描述: 在系统可编程3.3V SuperWIDE⑩高密度PLD [In-System Programmable 3.3V SuperWIDE⑩ High Density PLD]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 25 页 / 311 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications ispLSI 5256VA  
4mA and sink 8mA in 3.3V mode. The output drivers  
have a separate VCCIO reference input which is inde-  
pendent of the main VCC supply for the device. This  
feature allows the output drivers to drive either 3.3V or  
2.5V output levels while the device logic and the output  
current drive is always powered from 3.3V. The output  
drivers also provide individually programmable edge  
rates and open drain capability. A programmable pullup  
resistor is provided to tie off unused inputs and a pro-  
grammable bus-hold latch is available to hold tristate  
outputs in their last valid state until the bus is driven again  
by some device.  
ispLSI 5000V Description (Continued)  
in both true and complement form for every product term.  
The 160 product terms are grouped in 32 sets of five and  
sent into a Product Term Sharing Array (PTSA) which  
allows sharing up to a maximum of 35 product terms for  
a single function. Alternatively, the PTSA can be by-  
passed for functions of five product terms or less. The  
five extra product terms are used for shared GLB con-  
trols, set, reset, clock, clock enable and output enable.  
The32registeredmacrocellsintheGLBaredrivenbythe  
32 outputs from the PTSA or the PTSA bypass. Each  
macrocell contains a programmable XOR gate, a pro-  
grammable register/latch/toggle flip-flop and the  
necessary clocks and control logic to allow combinatorial  
or registered operation. The macrocells each have two  
outputs, which can be fed back through the Global  
Routing Pool. This dual output capability from the  
macrocell allows efficient use of the hardware resources.  
One output can be a registered function for example,  
while the other output can be an unrelated combinatorial  
function. A direct register input from the I/O pad facili-  
tates efficient use of this feature to construct high-speed  
input registers.  
The ispLSI 5000V Family features 3.3V, non-volatile in-  
system programmability for both the logic and the  
interconnect structures, providing the means to develop  
truly reconfigurable systems. Programming is achieved  
through the industry standard IEEE 1149.1-compliant  
Boundary Scan interface. Boundary Scan test is also  
supported through the same interface.  
An enhanced, multiple cell security scheme is provided  
that prevents reading of the JEDEC programming file  
when secured. After the device has been secured using  
this mechanism, the only way to clear the security is to  
execute a bulk-erase instruction.  
Macrocell registers can be clocked from one of several  
global or product term clocks available on the device. A  
global and product term clock enable is also provided,  
eliminating the need to gate the clock to the macrocell  
registers. Reset and preset for the macrocell register is  
provided from both global and product term signals. The  
macrocell register can be programmed to operate as a D-  
type register, a D-type latch or a T-type flip flop.  
ispLSI 5000V Family Members  
The ispLSI 5000V Family ranges from 256 macrocells to  
512 macrocells and operates from a 3.3V power supply.  
All family members will be available with multiple pack-  
age options. The ispLSI 5000V Family device matrix  
showingthevariousbondoutoptionsisshowninthetable  
below.  
The 32 outputs from the GLB can drive both the Global  
Routing Pool and the device I/O cells. The Global  
Routing Pool contains one line from each macrocell  
output and one line from each I/O pin.  
Theinterconnectstructure(GRP)isverysimilartoLattice's  
existing ispLSI 1000, 2000 and 3000 families, but with an  
enhanced interconnect structure for optimal pin locking  
and logic routing. This eliminates the need for registered  
I/O cells or an Output Routing Pool.  
The input buffer threshold has programmable TTL/3.3V/  
2.5V compatible levels. The output driver can source  
Table 1. ispLSI 5000V Family  
Package Type  
Device  
GLBs  
8
Macrocells 208 fpBGA  
208 PQFP  
144 I/O  
272 BGA  
192 I/O  
192 I/O  
192 I/O  
388 BGA  
ispLSI 5256VA  
ispLSI 5384VA  
ispLSI 5512VA  
256  
384  
512  
144 I/O  
144 I/O  
12  
144 I/O  
288 I/O  
288 I/O  
16  
144 I/O  
3