Specifications ispLSI 2064V
ispLSI 2064V Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
#20
#24
(Input)
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0,1
0491/2064
Derivations of tsu, th and t
co from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (tio + tgrp + tptck(min))
t
t
t
t
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
4.6 ns
= (0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
0.7 ns
co
= (0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)
t
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
10.1 ns
= (0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)
Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.
Table 2-0042/2064V
7
LATTICE [ LATTICE SEMICONDUCTOR ]
