Specifications ispGDX Family
Boundary Scan / ISP Programming and Test Options
The ispGDX devices provide IEEE1149.1a test capabil- are organized in the order given below. Each
ity and ISP programming through a standard Boundary I/O register is structured as shown in Figure 7.
Scan Test Access Port (TAP) interface. In addition,
The operation of the boundary scan test circuitry in the
ispGDX devices can be programmed via the Lattice ISP
ispGDX160isdependentonthefusepatternprogrammed
programming interface using the same TAP serial inter-
into the device. The boundary scan circuitry on the
face pins.
ispGDX160A, ispGDX120A and ispGDX80A operates
When the BSCAN/ispEN signal is high the ispGDX de- independently of the programmed pattern. This allows
vices enable Boundary Scan Test mode. Under this customers using boundary scan test to have full test
mode the Boundary Scan data registers for the I/O pins capability with only a single BSDL file.
Table 3. I/O Shift Register Order
DEVICE
I/O SHIFT REGISTER ORDER
ispGDX80A
SDI/TDI, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, RESET, Y1/TOE, Y0, I/O B9 .. B0, I/O A19.. A0,
I/O D19 .. D10, SDO/TDO
ispGDX120A
ispGDX160/A
SDI/TDI, I/O B15 .. B29, I/O C0 .. C29, I/O D0 .. D14, TOE, Y2, Y3, RESET, Y1, Y0, I/O B14 .. B0,
I/O A29.. A0, I/O D29 .. D15, SDO/TDO
SDI/TDI, I/O B20 .. B39, I/O C0 .. C39, I/O D0 .. D19, TOE, Y2, Y3, RESET, Y1, Y0, I/O B19 .. B0,
I/O A39.. A0, I/O D39 .. D20, SDO/TDO
I/O Shift Reg Order/ispGDX
Figure 7. Boundary Scan I/O Register Cell
Normal
Function
OE
M
U
X
TOE
SCANIN
M
(from
Q
Q
Q
Q
D
D
D
D
U
X
previous
cell)
EXTEST
Normal
Function
OE
M
U
X
I/O Pin
M
U
X
Q
D
Update DR
M
U
X
SCANOUT (to next cell)
Shift DR
Clock DR
14
LATTICE [ LATTICE SEMICONDUCTOR ]
