GAL26CLV12
Low Voltage E
2
CMOS PLD
Generic Array Logic™
FEATURES
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 200 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— Inputs and I/O Interface with Standard 5V TTL Devices
• ACTIVE PULL-UPS ON ALL PINS
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
Functional Block Diagram
I/CLK
RESET
INPUT
8
I
8
I
8
I
8
I
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(122X52)
OLMC
I/O/Q
10
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
I
8
I
8
I
8
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
PRESET
I/O/Q
Description
The GAL26CLV12D, at 5 ns maximum propagation delay time,
provides higher performance than its 5V counterpart. The
GAL26CLV12D can interface with both 3.3V and 5V signal levels.
The GAL26CLV12D is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/O/Q
I/O/Q
26
25
I
I
2
4
I
I
I
VCC
I
I
I
I
5
I
28
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
7
GAL26CLV12D
Top View
23
9
21
11
12
14
16
19
18
I/O/Q
I/O/Q
I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I
I
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
26clv12_02
1
LATTICE [ LATTICE SEMICONDUCTOR ]
