Specifications GAL26CV12
Output Logic Macrocell (OLMC)
The GAL26CV12 has a variable number of product terms per The GAL26CV12 has a product term forAsynchronous Reset (AR)
OLMC. Of the twelve available OLMCs, two OLMCs have access and a product term for Synchronous Preset (SP). These two prod-
to twelve product terms (pins 20 and 22), two have access to ten uct terms are common to all registered OLMCs. TheAsynchronous
product terms (pins 19 and 23), and the other eight OLMCs have Reset sets all registered outputs to zero any time this dedicated
eight product terms each. In addition to the product terms available product term is asserted. The Synchronous Preset sets all registers
for logic, each OLMC has an additional product term dedicated to to a logic one on the rising edge of the next clock pulse after this
output enable control.
product term is asserted.
The output polarity of each OLMC can be individually programmed NOTE: TheAR and SP product terms will force the Q output of the
to be true or inverting, in either combinatorial or registered mode. flip-flop into the same state regardless of the polarity of the output.
This allows each output to be individually configured as either active Therefore, a reset operation, which sets the register output to a zero,
high or active low.
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
A R
D
4 T O
1
Q
Q
M U X
C L K
S P
2 T O
1
M U X
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL26CV12 has two primary NOTE: In registered mode, the feedback is from the /Q output of
functional modes: registered, and combinatorial I/O. The modes the register, and not from the pin; therefore, a pin defined as
and the output polarity are set by two bits (SO and S1), which are registered is an output only, and cannot be used for dynamic
normally controlled by the logic compiler. Each of these two primary I/O, as can the combinatorial pins.
modes, and the bit settings required to enable them, are described
below and on the the following page.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
REGISTERED
In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the output
OLMC is driven by the Q output of that OLMC’s D-type flip-flop. buffer drive either true (active high) or inverted (active low). Output
Logic polarity of the output signal at the pin may be selected by tri-state control is available as an individual product term for each
specifying that the output buffer drive either true (active high) or output, and may be individually set by the compiler as either “on”
inverted (active low). Output tri-state control is available as an (dedicated output), “off” (dedicated input), or “product term driven”
individual product term for each OLMC, and can therefore be (dynamic I/O). Feedback into theAND array is from the pin side of
defined by a logic equation. The D flip-flop’s /Q output is fed back the output enable buffer. Both polarities (true and inverted) of the
into the AND array, with both the true and complement of the pin are fed back into the AND array.
feedback available as inputs to the AND array.
3
LATTICE [ LATTICE SEMICONDUCTOR ]
