Specifications GAL26CV12
fmax Definitions
C L K
CLK
LOGIC
ARRAY
LOGIC
ARR AY
REGISTER
REGISTER
t
su
tco
fmax with External Feedback 1/(tsu+tco)
t
cf
pd
t
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
CLK
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
LOGIC
REGISTER
ARRAY
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
1.5ns 10% – 90%
3ns 10% – 90%
+5V
C-7/-10/-15
B-10/-15/-20
R
1
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
C L*
GAL26CV12 Output Load Conditions (see figure)
R
2
Test Condition
R1
R2
CL
A
300Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
B
Active High
Active Low
Active High
Active Low
300Ω
∞
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
300Ω
5pF
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