Specifications GAL22V10
Output Logic Macrocell (OLMC)
The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and
21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an addi-
tional product-term dedicated to output enable control.
The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. TheAsynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: TheAR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
A R
D
4 T O
1
Q
M U X
C L K
Q
S P
2 T O
1
M U X
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL22V10 has two primary functional NOTE: In registered mode, the feedback is from the /Q output of
modes: registered, and combinatorial I/O. The modes and the the register, and not from the pin; therefore, a pin defined as reg-
output polarity are set by two bits (SO and S1), which are normally istered is an output only, and cannot be used for dynamic
controlled by the logic compiler. Each of these two primary modes, I/O, as can the combinatorial pins.
and the bit settings required to enable them, are described below
and on the following page.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
REGISTERED
In registered mode the output pin associated with an individual output signal at the pin may be selected by specifying that the output
OLMC is driven by the Q output of that OLMC’s D-type flip-flop. buffer drive either true (active high) or inverted (active low). Out-
Logic polarity of the output signal at the pin may be selected by put tri-state control is available as an individual product-term for
specifying that the output buffer drive either true (active high) or each output, and may be individually set by the compiler as either
inverted (active low). Output tri-state control is available as an in- “on” (dedicated output), “off” (dedicated input), or “product-term
dividual product-term for each OLMC, and can therefore be defined driven” (dynamic I/O). Feedback into theAND array is from the pin
by a logic equation. The D flip-flop’s /Q output is fed back into the side of the output enable buffer. Both polarities (true and inverted)
AND array, with both the true and complement of the feedback of the pin are fed back into the AND array.
available as inputs to the AND array.
3
LATTICE [ LATTICE SEMICONDUCTOR ]
