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GAL22V10D-25LPI 参数 Datasheet PDF下载

GAL22V10D-25LPI图片预览
型号: GAL22V10D-25LPI
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 29 页 / 387 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL22V10  
Power-Up Reset  
Vcc (min.)  
Vcc  
t
su  
CLK  
t
wl  
t
pr  
Internal Register  
Reset to Logic "0"  
INTERNAL REGISTER  
Q - OUTPUT  
ACTIVE LOW  
OUTPUT REGISTER  
Device Pin  
Reset to Logic "1"  
Device Pin  
Reset to Logic "0"  
ACTIVE HIGH  
OUTPUT REGISTER  
Circuitry within the GAL22V10 provides a reset signal to all reg-  
isters during power-up. All internal registers will have their Q out-  
puts set low after a specified time (tpr, 1µs MAX). As a result, the  
state on the registered output pins (if they are enabled) will be  
either high or low on power-up, depending on the programmed  
polarity of the output pins. This feature can greatly simplify state  
machine design by providing a known state on power-up. The  
timing diagram for power-up is shown below. Because of the asyn-  
chronous nature of system power-up, some conditions must be  
met to guarantee a valid power-up reset of the GAL22V10. First,  
the Vcc rise must be monotonic. Second, the clock input must  
be at static TTL level as shown in the diagram during power up.  
The registers will reset within a maximum of tpr time. As in nor-  
mal system operation, avoid clocking the device until all input and  
feedback path setup times have been met. The clock must also  
meet the minimum pulse width requirements.  
Input/Output Equivalent Schematics  
PIN  
PIN  
Feedback  
Vcc  
Active Pull-up  
Circuit  
Active Pull-up  
Circuit  
(Vref Typical = 3.2V)  
(Vref Typical = 3.2V)  
Vcc  
Tri-State  
Control  
Vcc  
Vcc  
Vref  
Vref  
ESD  
Protection  
Circuit  
PIN  
Data  
Output  
PIN  
ESD  
Protection  
Circuit  
Feedback  
(To Input Buffer)  
Typical Input  
Typical Output  
17  
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