Specifications GAL22LV10
POWER-UP RESET
Vcc (min.)
Vcc
tsu
twl
CLK
tpr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
ACTIVE HIGH
OUTPUT REGISTER
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL22V10. First, the
Vcc rise must be monotonic. Second, the clock input must be at
static TTL level as shown in the diagram during power up. The
registers will reset within a maximum of tpr time. As in normal sys-
tem operation, avoid clocking the device until all input and feed-
back path setup times have been met. The clock must also meet
the minimum pulse width requirements.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
PIN
Feedback
Vcc
Active Pull-up Circuit
(GAL22LV10D Only)
Active Pull-up Circuit
(GAL22LV10D Only)
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typ. Vref = Vcc
Typ. Vref = Vcc
Typical Input
Typical Output
14
LATTICE [ LATTICE SEMICONDUCTOR ]
