Ne
Tolew 5V
Inp rant
22Luts on
V10
D
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
(GAL22LV10C)
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
I
GAL22LV10
Low Voltage E
2
CMOS PLD
Generic Array Logic™
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
OLMC
I
12
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
14
OLMC
I/O/Q
16
OLMC
I
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
PRESET
Description
The GAL22LV10D, at 4 ns maximum propagation delay time, pro-
vides the highest speed performance available in the PLD market.
The GAL22LV10C can interface with both 3.3V and 5V signal levels.
The GAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/O/Q
Vcc
NC
I/O/Q
I
4
I
I
I
NC
I
I
I
11
12
I
I
I
2
28
26
25
I/O/Q
I/O/Q
5
7
GAL22LV10
Top View
23
I/O/Q
NC
9
21
I/O/Q
I/O/Q
14
GND
NC
16
I
I/O/Q
19
18
I/O/Q
I/O/Q
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 2000
22lv10_04
1
LATTICE [ LATTICE SEMICONDUCTOR ]
