Specifications GAL20V8
Power-Up Reset
Vcc (min.)
Vcc
t
su
t
wl
CLK
t
pr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL20V8 provides a reset signal to all registers a valid power-up reset of the device. First, the VCC rise must be
during power-up. All internal registers will have their Q outputs set monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
low after a specified time (tpr, 1µs MAX). As a result, the state on
the registered output pins (if they are enabled) will always be high
on power-up, regardless of the programmed polarity of the output clocking the device until all input and feedback path setup times
pins. This feature can greatly simplify state machine design by pro- have been met. The clock must also meet the minimum pulse width
viding a known state on power-up. Because of the asynchronous requirements.
nature of system power-up, some conditions must be met to provide
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Active Pull-up
Circuit
Active Pull-up
Circuit
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typ. Vref = 3.2V
Typ. Vref = 3.2V
Typical Input
Typical Output
17
LATTICE [ LATTICE SEMICONDUCTOR ]
