Specifications GAL20RA10
Power-Up Reset
Vcc (min.)
Vcc
tsu
twl
CLK
tpr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL20RA10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous
nature of system power-up, some conditions must be met to
provide a valid power-up reset of the GAL20RA10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The regis-
ters will reset within a maximum of 1µs. As in normal system op-
eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Active Pull-up
Circuit
Vcc
(Vref Typical = 3.2V)
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
11
LATTICE [ LATTICE SEMICONDUCTOR ]
