Specifications GAL20RA10
Output Logic Macrocell (OLMC)
Asynchronous Reset and Preset
The GAL20RA10 OLMC consists of 10 D flip-flops with indi- Each GAL20RA10 macrocell has an independent asynchronous
vidual asynchronous programmable reset, preset and clock product reset and preset control product term. The reset and preset product
terms. The sum of four product terms and an Exclusive-OR pro- terms are level sensitive, and will hold the flip-flop in the reset or
vide a programmable polarity D-input to each flip-flop. An output preset state while the product term is active independent of the clock
enable term combined with the dedicated output enable pin pro- or D-inputs. It should be noted that the reset and preset term al-
vides tri-state control of each output. Each OLMC has a flip-flop ter the state of the flip-flop whose output is inverted by the output
bypass, allowing any combination of registered or combinatorial buffer. A reset of the flip-flop will result in the output pin becoming
outputs.
a logic high and a preset will result in a logic low.
The GAL20RA10 has 10 dedicated input pins and 10 program-
mable I/O pins, which can be either inputs, outputs, or dynamic I/
O. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange I/O pin assignments without restric-
tion.
RESET PRESET
FUNCTION
0
1
0
1
0
0
1
1
Registered function of data product term
Reset register to "0" (device pin = "1")
Preset register to "1" (device pin = "0")
Register-bypass (combinatorial output)
Independent Programmable Clocks
Combinatorial Control
An independent clock control product term is provided for each
GAL20RA10 macrocell. Data is clocked into the flip-flop on the
active edge of the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These clocks
can be derived from any pin or combination of pins and/or feedback
from other flip-flops. Multiple clock sources allow a number of
asynchronous register functions to be combined into a single
GAL20RA10. This allows the designer to combine discrete logic
functions into a single device.
The register in each GAL20RA10 macrocell may be bypassed by
asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell as
a combinatorial output, or to fix the macrocell as combinatorial only
by forcing both reset and preset product terms active. Some logic
compilers will configure macrocells as registered or combinatorial
based on the logic equations, others require the designer to force
the reset and preset product terms active for combinatorial
macrocells.
Programmable Polarity
The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flip-
flop. The polarity of the pin is active low when XOR bit is pro-
grammed (or zero) and is active high when XOR bit is erased (or
one). Because of the inverted output buffer, the XOR gate output
node is opposite polarity from the pin. It should be noted that the
programmable polarity only affects the data latched into the flip-flop
on the active edge of the clock product term. The reset, preset and
preload will alter the state of the flip-flop independent of the state
of programmable polarity bit. The ability to program the active po-
larity of the D-inputs can be used to reduce the total number of
product terms used, by allowing the DeMorganization of the logic
functions. This logic reduction is accomplished by the logic com-
piler, and does not require the designer to define the polarity.
Parallel Flip-Flop Preload
The flip-flops of a GAL20RA10 can be reset or preset from the
I/O pins by applying a logic low to the preload pin (pin 1 on DIP
package / pin 2 on PLCC package) and applying the desired logic
level to each I/O pin. The I/O pins must remain valid for the preload
setup and hold time. All 10 flip-flops are reset or preset during
preload, independent of all other OLMC inputs.
A logic low on an I/O pin during preload will preset the flip-flop, a
logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin will disable all 10 outputs of the
GAL20RA10 when held high.
Output Enable
The output of each GAL20RA10 macrocell is controlled by the
“AND’ing” of an independent output enable product term and a
common active low output enable pin (pin 13 on DIP package / pin
16 on PLCC package). The output is enabled while the output en-
able product term is active and the output enable pin is low. This
output control structure allows several output enable alternatives.
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LATTICE [ LATTICE SEMICONDUCTOR ]
