Specifications GAL20RA10
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
REGISTER
ARRAY
t
su
tco
fmax with No Feedback
fmax with External Feedback 1/(tsu+tco)
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
+5V
-7/-10
2ns 10% – 90%
3ns 10% – 90%
1.5V
-15/-20/-30
R
1
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
C L*
R
2
Output Load Conditions (see figure)
Test Condition
R1
R2
CL
A
B
470Ω
∞
470Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
Active High
Active Low
Active High
Active Low
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
470Ω
5pF
9
LATTICE [ LATTICE SEMICONDUCTOR ]
