GAL20VP8B-25LJ 参数 Datasheet PDF下载

GAL20VP8

High-Speed E

2

CMOS PLD

Generic Array Logic™

Features

• HIGH DRIVE E

2

CMOS

®

GAL

®

DEVICE

— TTL Compatible 64 mA Output Drive

— 15 ns Maximum Propagation Delay

— Fmax = 80 MHz

— 10 ns Maximum from Clock Input to Data Output

— UltraMOS

®

Advanced CMOS Technology

• ENHANCED INPUT AND OUTPUT FEATURES

— Schmitt Trigger Inputs

— Programmable Open-Drain or Totem-Pole Outputs

— Active Pull-Ups on All Inputs and I/O pins

• E

2

CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Compatible with Standard GAL20V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Ideal for Bus Control & Bus Arbitration Logic

— Bus Address Decode Logic

— Memory Address, Data and Control Circuits

— DMA Control

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I

8

I

OLMC

I/O/Q

Functional Block Diagram

I/CLK

I

I

IMUX

CLK

8

OLMC

I/O/Q

PROGRAMMABLE

AND-ARRAY

(64 X 40)

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

OLMC

I/O/Q

I

8

I

8

OLMC

OE

OLMC

I/O/Q

I/O/Q

I

I

I

IMUX

I/OE

Description

The GAL20VP8, with 64 mA drive capability and 15 ns maximum

propagation delay time is ideal for Bus and Memory control appli-

cations.

The GAL20VP8 is manufactured using Lattice

Semiconductor's advanced E

2

CMOS process which combines

CMOS with Electrically Erasable (E

2

) floating gate technology. High

speed erase times (<100ms) allow the devices to be reprogrammed

quickly and efficiently.

System bus and memory interfaces require control logic before

driving the bus or memory interface signals. The GAL20VP8

combines the familiar GAL20V8 architecture with bus drivers as

its outputs. The generic architecture provides maximum design flex-

ibility by allowing the Output Logic Macrocell (OLMC) to be con-

figured by the user. The 64mA output drive eliminates the need for

additional devices to provide bus-driving capability.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

Pin Configuration

PLCC

I/CLK

I/CLK

I/O/Q

NC

DIP

1

24

I

I

I/O/Q

I

I

25

I/O/Q

I/O/Q

I

I

28

4

I

I

Vcc

NC

I

I

I

11

12

9

7

5

I

2

I

26

I

I

Vcc

I

I

I

I

I

I/OE

12

6

GAL

20VP8

18

I/O/Q

I/O/Q

I/O/Q

GND

I/O/Q

I/O/Q

I/O/Q

I/O/Q

13

I

GAL20VP8

Top View

14

16

23

I/O/Q

NC

21

GND

I/O/Q

19

18

I/O/Q

I/OE

I/O/Q

Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

I/O/Q

I

I

NC

I

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

20vp8_03

1