欢迎访问ic37.com |
会员登录 免费注册
发布采购

GAL20V8ZD-15QP 参数 Datasheet PDF下载

GAL20V8ZD-15QP图片预览
型号: GAL20V8ZD-15QP
PDF下载: 下载PDF文件 查看货源
内容描述: 零功率E2CMOS PLD [Zero Power E2CMOS PLD]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 19 页 / 307 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第7页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第8页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第9页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第10页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第12页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第13页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第14页浏览型号GAL20V8ZD-15QP的Datasheet PDF文件第15页  
Specifications GAL20V8Z  
AC Switching Characteristics  
Over Recommended Operating Conditions  
COM  
-12  
COM  
-15  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX.  
MIN. MAX.  
tpd  
tco  
tcf2  
tsu  
th  
A
A
Input or I/O to Combinational Output  
3
2
12  
8
3
2
15  
10  
7
ns  
ns  
ns  
ns  
Clock to Output Delay  
Clock to Feedback Delay  
10  
6
15  
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
A
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
55  
40  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
62.5  
83.3  
45.5  
62.5  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
6
6
8
8
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
OE to Output Enabled  
12  
12  
15  
15  
ns  
ns  
tdis  
C
C
Input or I/O to Output Disabled  
OE to Output Disabled  
15  
12  
15  
15  
ns  
ns  
tas  
tsa4  
Last Active Input to Standby  
Standby to Active Output  
60  
6
140  
13  
50  
5
150  
15  
ns  
ns  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Specification section.  
3) Refer to fmax Specification section.  
4) Add tsa to tpd, tsu, ten and tdis when the device is coming out of standby state.  
Standby Power Timing Waveforms  
Icc  
POWER  
Isb  
t
as  
t
sa  
tpd  
INPUT or  
I/O FEEDBACK  
t
en, tdis  
OE  
t
su  
*
* Note: Rising clock edges  
are allowed during sa but  
outputs are not guaranteed.  
t
CLK  
t
co  
OUTPUT  
11