Specifications GAL20V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-
registered outputs or as I/O functions. sets of the I/O function.
Architecture configurations available in this mode are similar to the Registered outputs have eight product terms per output. I/Os have
common 20R8 and 20RP4 devices with various permutations of seven product terms per output.
polarity, I/O and register placement.
The JEDEC fuse numbers, including the User Electronic Signature
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown
control pins. Any macrocell can be configured as registered or I/ on the logic diagram on the following page.
O. Up to eight registers or up to eight I/Os are possible in this mode.
CLK
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
D
Q
Q
- Pin 1 controls common CLK for the registered outputs.
XOR
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE for registered output configuration.
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
XOR
OE for registered output configuration..
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
5
LATTICE [ LATTICE SEMICONDUCTOR ]
