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GAL20LV8ZD 参数 Datasheet PDF下载

GAL20LV8ZD图片预览
型号: GAL20LV8ZD
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压,零功率E2CMOS PLD通用阵列逻辑 [Low Voltage, Zero Power E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 18 页 / 284 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL20LV8ZD  
Dedicated Power-Down Pin Specications  
Over Recommended Operating Conditions  
COM  
-15  
COM  
-25  
TEST  
DESCRIPTION  
PARAMETER  
UNITS  
COND1.  
MIN. MAX.  
MIN. MAX.  
twhd  
twld  
DPP Pulse Duration High  
DPP Pulse Duration Low  
40  
30  
40  
40  
ns  
ns  
ACTIVE TO STANDBY  
tivdh  
tgvdh  
tcvdh  
tdhix  
Valid Input before DPP High  
Valid OE before DPP High  
0
0
15  
15  
15  
0
0
25  
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
Valid Clock before DPP High  
Input Don't Care after DPP High  
OE Don't Care after DPP High  
Clock Don't Care after DPP High  
0
0
tdhgx  
tdhcx  
STANDBY TO ACTIVE  
tixdl  
tgxdl  
tcxdl  
tdliv  
A
Input Don't Care before DPP Low  
OE Don't Care before DPP Low  
Clock Don't Care before DPP Low  
DPP Low to Valid Input  
20  
20  
30  
5
0
0
25  
25  
35  
5
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0
0
45  
45  
tdlgv  
tdlcv  
tdlov  
DPP Low to Valid OE  
DPP Low to Valid Clock  
DPP Low to Valid Output  
1) Refer to Switching Test Conditions section.  
Dedicated Power-Down Pin Timing Waveforms  
DPP  
t
t
ivdh  
t
dhix  
t
ixdl  
t
t
dliv  
INPUT or  
I/O FEEDBACK  
gvdh  
t
dhgx  
t
gxdl  
dlgv  
OE  
t
cvdh  
t
dhcx  
t
cxdl  
t
dlcv  
CLK  
t
c o  
t
pd,t  
en,tdis  
tdlov  
OUTPUT  
12