Specifications GAL16VP8
Power-Up Reset
Vcc (min.)
Vcc
tsu
twl
CLK
tpr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
of system power-up, some conditions must be met to provide a valid
power-up reset of the GAL16VP8. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Circuitry within the GAL16VP8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown above. Because of the asynchronous nature
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Vcc
Active Pull-up
Circuit
Active Pull-up
Circuit
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Vref = 3.1V
Vref = 3.1V
Typical Input
Typical Output
15
LATTICE [ LATTICE SEMICONDUCTOR ]
