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GAL16V811111 参数 Datasheet PDF下载

GAL16V811111图片预览
型号: GAL16V811111
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 23 页 / 395 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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SpecificationsGAL16V8C
AC SWITCHING CHARACTERISTICS  
Over Recommended Operating Conditions  
COM  
-5  
COM  
-7  
IND  
-7  
TEST  
COND1.  
DESCRIPTION  
PARAMETER  
UNITS  
MIN. MAX.  
MIN. MAX.  
MIN. MAX.  
tpd  
A
Input or I/O to  
Comb. Output  
8 outputs switching  
1 output switching  
1
5
3
7.5  
7
1
7.5  
ns  
ns  
tco  
tcf2  
tsu  
th  
A
Clock to Output Delay  
1
3
4
3
2
7
5
3
1
7
5
3
ns  
ns  
ns  
Clock to Feedback Delay  
Setup Time, Input or Feedback before Clock↑  
Hold Time, Input or Feedback after Clock↑  
A
0
0
0
ns  
Maximum Clock Frequency with  
External Feedback, 1/(tsu + tco)  
142.8 —  
83.3  
83.3  
MHz  
fmax3  
A
A
Maximum Clock Frequency with  
Internal Feedback, 1/(tsu + tcf)  
166  
166  
100  
100  
100  
100  
MHz  
MHz  
Maximum Clock Frequency with  
No Feedback  
twh  
twl  
Clock Pulse Duration, High  
Clock Pulse Duration, Low  
3
3
5
5
5
5
ns  
ns  
ten  
B
B
Input or I/O to Output Enabled  
OE to Output Enabled  
1
1
6
6
3
2
9
6
1
1
9
6
ns  
ns  
tdis  
C
C
Input or I/O to Output Disabled  
OE to Output Disabled  
1
1
5
5
2
9
6
1
1
9
6
ns  
ns  
1.5  
1) Refer to Switching Test Conditions section.  
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.  
3) Refer to fmax Descriptions section. Characterized initially and after any design or process changes that may affect these  
parameters.  
CAPACITANCE (TA = 25°C, f = 1.0 MHz)  
SYMBOL  
PARAMETER  
Input Capacitance  
I/O Capacitance  
MAXIMUM*  
UNITS  
pF  
TEST CONDITIONS  
VCC = 5.0V, VI = 2.0V  
VCC = 5.0V, VI/O = 2.0V  
CI  
8
8
CI/O  
pF  
*Guaranteed but not 100% tested.  
1996 Data Book  
3-75