Specifications GAL16VP8
fmax Descriptions
CLK
LOGIC
ARRAY
CLK
REGISTER
LOGIC
ARRAY
REGISTER
t
su
tco
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated
from measured tsu and tco.
t
cf
pd
t
fmax with Internal Feedback 1/(tsu+tcf)
CLK
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf
LOGIC
REGISTER
ARRAY
is used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
t
su + th
natorial output is equal to tcf + tpd.
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
+5V
Input Pulse Levels
GND to 3.0V
3ns 10% – 90%
1.5V
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
R
1
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
Test Condition
R1
R2
CL
C L*
R
2
A
B
500Ω
∞
500Ω
∞
500Ω
500Ω
500Ω
500Ω
500Ω
50pF
50pF
50pF
5pF
Active High
Active Low
Active High
Active Low
C
500Ω
5pF
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
13
LATTICE [ LATTICE SEMICONDUCTOR ]
